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Digest of Papers IEEE International Workshop on IDDQ Testing最新文献

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A comprehensive wafer oriented test evaluation (WOTE) scheme for the IDDQ testing of deep sub-micron technologies 一种用于深亚微米IDDQ测试的晶圆定向测试综合评估(WOTE)方案
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633011
A. Singh
{"title":"A comprehensive wafer oriented test evaluation (WOTE) scheme for the IDDQ testing of deep sub-micron technologies","authors":"A. Singh","doi":"10.1109/IDDQ.1997.633011","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633011","url":null,"abstract":"As device dimensions approach 0.1 /spl mu/m, analog effects will play an even larger role in digital circuits. IDDQ measurements can be significantly affected by the observed wafer to wafer (and even die to die) variations in electrical parameters. In this presentation we make a case for a Wafer Oriented Test Evaluation (WOTE) strategy where acceptable IDDQ thresholds are set based on the IDDQ measurements observed for the neighbouring die. Such an approach will minimize yield loss due to IDDQ testing while identifying defective die with abnormal IDDQ in comparison with their neighbours.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131795102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Detecting bridging faults in dynamic CMOS circuits 动态CMOS电路中的桥接故障检测
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633022
J.T.-Y. Chang, E. McCluskey
{"title":"Detecting bridging faults in dynamic CMOS circuits","authors":"J.T.-Y. Chang, E. McCluskey","doi":"10.1109/IDDQ.1997.633022","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633022","url":null,"abstract":"New methods for detecting bridging faults in dynamic CMOS circuits are proposed. We show that resistive shorts in CMOS dynamic circuits can cause intermittent failures and reliability problems. We found that the defect coverage of resistive shorts, which we defined as the maximum detectable resistance of a short, in CMOS domino gates, can be improved by increasing the supply voltage to be about 40% higher than the normal operating voltage or by reducing the supply voltage to about 2V/sub t/, where V/sub t/ is the threshold voltage of a transistor.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"490 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113986642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
I/sub DDQ/ testing for submicron CMOS IC technology qualification I/sub DDQ/测试用于亚微米CMOS IC技术鉴定
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633013
J. Soden
{"title":"I/sub DDQ/ testing for submicron CMOS IC technology qualification","authors":"J. Soden","doi":"10.1109/IDDQ.1997.633013","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633013","url":null,"abstract":"Sandia is manufacturing high reliability CMOS ICs with a 0.5 micron CMP technology, as part of the progression to 0.35 micron and smaller scale technologies. To qualify this technology for delivery of high reliability ICs to customers for military, space, and commercial applications, a qualification program has been implemented that includes extensive loop testing. Two vehicles are being used for this qualification, a 256 K bit SRAM and a Microcontroller Core (MCC). Both of these ICs present unique loop testing challenges. This paper describes the methods used to successfully implement I/sub DDQ/ testing for these two types of ICs.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124093922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Sequential circuit test generation for IDDQ testing of bridging faults 顺序电路测试生成用于IDDQ测试桥接故障
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633006
Y. Higamit, T. Maeda, K. Kinoshita
{"title":"Sequential circuit test generation for IDDQ testing of bridging faults","authors":"Y. Higamit, T. Maeda, K. Kinoshita","doi":"10.1109/IDDQ.1997.633006","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633006","url":null,"abstract":"This paper presents a test generation method for sequential circuits assuming IDDQ testing. We consider external bridging faults and internal bridging faults as a target fault. Test generation for external bridging faults consists of three phases as (1) use of weighted random vectors, (2) set of target values on selected signal lines, (3) deterministic test generation for undetected faults. In order to detect internal bridging faults, we use a sequential test generator for stuck-at-faults. Finally experimental results for ISCAS'89 benchmark circuits are given.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116151989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A hybrid (logic+I/sub DDQ/) testing strategy using an iterative bridging fault filtering scheme 采用迭代桥接故障滤波方案的混合(逻辑+I/sub DDQ/)测试策略
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633015
Tzuhao Chen, I. Hajj
{"title":"A hybrid (logic+I/sub DDQ/) testing strategy using an iterative bridging fault filtering scheme","authors":"Tzuhao Chen, I. Hajj","doi":"10.1109/IDDQ.1997.633015","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633015","url":null,"abstract":"In this paper we propose a new hybrid (logic+I/sub DDQ/) testing strategy for efficient bridging fault (BF) detection. In our strategy, logic and I/sub DDQ/ testings are applied in sequence so that BFs that can be detected by the logic testing need not be targeted by the I/sub DDQ/ testing. The logic test generation is done via an iterative BF filtering in which fault coverage is maximized through test set augmentation. As a result only a small number of BFs need to be targeted by the I/sub DDQ/ test generator. Experiments show that this approach is capable of reaching very high BF coverage with a composite (logic+I/sub DDQ/) test set with very few I/sub DDQ/ vectors.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116809029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A current sensing circuit for feedback bridging faults 一种用于反馈桥接故障的电流传感电路
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633023
M. Hashizume, M. Ichimiya, T. Tamesada
{"title":"A current sensing circuit for feedback bridging faults","authors":"M. Hashizume, M. Ichimiya, T. Tamesada","doi":"10.1109/IDDQ.1997.633023","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633023","url":null,"abstract":"In this paper, a supply current sensing circuit for detecting feedback bridging faults, which generates oscillations when a sensitized input is provided, is proposed. The circuit consists of an I-V transformer, a high-frequency amplifier and a demodulation circuit. It is shown by some experiments that such bridging faults can be detected with the circuit.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132412882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Current-mode techniques for self-testing analogue circuits 自测试模拟电路的电流模式技术
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633010
I. Baturone, S. Sánchez-Solano, A. Richardson, J. Huertas
{"title":"Current-mode techniques for self-testing analogue circuits","authors":"I. Baturone, S. Sánchez-Solano, A. Richardson, J. Huertas","doi":"10.1109/IDDQ.1997.633010","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633010","url":null,"abstract":"The success of I/sub ddq/ testing for digital circuits has motivated several groups to investigate if the same or a similar method could be applied to analogue domain. The diverse behavior of analogue circuits regarding quiescent current and the problem of global variations in nominal values are serious handicaps in obtaining a generic current-mode test method to be applied off chip. A promising test procedure is the built-in self-testing (BIST) technique for which circuits with class A behavior are specially suited. This paper focuses on these type of circuits and in particular those based on symmetric OTAs. Two BIST techniques that permit low silicon area overheads, low voltage operation, and negligible influence on the circuit performance are proposed and discussed. Hspice simulations from a 5th order OTA-C elliptic filter show that global fault coverages of 92.2% and 96.6% are achieved by the two techniques.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115122713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Iddq test pattern generation for scan chain latches and flip-flops 扫描链锁存器和触发器Iddq测试模式生成
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633004
S. Makar, E. McCluskey
{"title":"Iddq test pattern generation for scan chain latches and flip-flops","authors":"S. Makar, E. McCluskey","doi":"10.1109/IDDQ.1997.633004","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633004","url":null,"abstract":"A new approach, using Iddq, for testing the bistable elements (latches ad flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking experiment to each bistable element in the circuit while checking their response. Such tests guarantee the detection of all detectable combinational defects inside the bistable elements. We show that this approach is more effective than test generation using the popular pseudo stuck-at-fault model. Our algorithm was implemented by modifying an existing stuck-at combinational test pattern generator. The number of test patterns generated by the new program is comparable to the number of traditional stuck-at-patterns. This shows that our approach is practical for large circuits.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115079152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
I/sub DDQ/ testing of a 180 MHz HP PA-RISC microprocessor with redundancy programmed caches 带有冗余编程缓存的180 MHz HP PA-RISC微处理器的I/sub DDQ/测试
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633012
T. Meneghini, D. Josephson
{"title":"I/sub DDQ/ testing of a 180 MHz HP PA-RISC microprocessor with redundancy programmed caches","authors":"T. Meneghini, D. Josephson","doi":"10.1109/IDDQ.1997.633012","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633012","url":null,"abstract":"The Hewlett-Packard PA7300LC is a 180 MHz PA-RISC microprocessor consisting of 1.2 million core logic transistors and 8 million cache transistors. The design of the power distribution network for this chip allowed independent measurement of the I/sub DDQ/ current for both the cache and the core logic of the chip. A test method was developed whereby it was possible to distinguish cache I/sub DDQ/ data resulting from a cache that was free from defects or was repaired through redundancy programming. The authors collected I/sub DDQ/ data from over fifty thousand parts and an analysis of this data is presented along with some conclusions.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115669178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Random testing with partial circuit duplication and monitoring I/sub DDQ/ 随机测试与部分电路重复和监测I/sub DDQ/
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633005
H. Yokoyama, X. Wen, H. Tamamoto
{"title":"Random testing with partial circuit duplication and monitoring I/sub DDQ/","authors":"H. Yokoyama, X. Wen, H. Tamamoto","doi":"10.1109/IDDQ.1997.633005","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633005","url":null,"abstract":"The advantage of random testing is that test application can be performed at a low cost in the BIST scheme. However, not all circuits are random pattern testable. In this paper, we present a method for improving random pattern testability of logic circuits by partial circuit duplication. The basic idea is to detect random pattern resistant faults by using the difference between the duplicated part of a circuit and the original part and detect the difference by monitoring I/sub DDQ/. Experimental results on benchmark circuits show that high fault coverage can be achieved with a very small amount of hardware overhead.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121792557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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