{"title":"动态CMOS电路中的桥接故障检测","authors":"J.T.-Y. Chang, E. McCluskey","doi":"10.1109/IDDQ.1997.633022","DOIUrl":null,"url":null,"abstract":"New methods for detecting bridging faults in dynamic CMOS circuits are proposed. We show that resistive shorts in CMOS dynamic circuits can cause intermittent failures and reliability problems. We found that the defect coverage of resistive shorts, which we defined as the maximum detectable resistance of a short, in CMOS domino gates, can be improved by increasing the supply voltage to be about 40% higher than the normal operating voltage or by reducing the supply voltage to about 2V/sub t/, where V/sub t/ is the threshold voltage of a transistor.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"490 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Detecting bridging faults in dynamic CMOS circuits\",\"authors\":\"J.T.-Y. Chang, E. McCluskey\",\"doi\":\"10.1109/IDDQ.1997.633022\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"New methods for detecting bridging faults in dynamic CMOS circuits are proposed. We show that resistive shorts in CMOS dynamic circuits can cause intermittent failures and reliability problems. We found that the defect coverage of resistive shorts, which we defined as the maximum detectable resistance of a short, in CMOS domino gates, can be improved by increasing the supply voltage to be about 40% higher than the normal operating voltage or by reducing the supply voltage to about 2V/sub t/, where V/sub t/ is the threshold voltage of a transistor.\",\"PeriodicalId\":429650,\"journal\":{\"name\":\"Digest of Papers IEEE International Workshop on IDDQ Testing\",\"volume\":\"490 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-11-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers IEEE International Workshop on IDDQ Testing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IDDQ.1997.633022\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers IEEE International Workshop on IDDQ Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IDDQ.1997.633022","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Detecting bridging faults in dynamic CMOS circuits
New methods for detecting bridging faults in dynamic CMOS circuits are proposed. We show that resistive shorts in CMOS dynamic circuits can cause intermittent failures and reliability problems. We found that the defect coverage of resistive shorts, which we defined as the maximum detectable resistance of a short, in CMOS domino gates, can be improved by increasing the supply voltage to be about 40% higher than the normal operating voltage or by reducing the supply voltage to about 2V/sub t/, where V/sub t/ is the threshold voltage of a transistor.