I/sub DDQ/ testing for submicron CMOS IC technology qualification

Abstract

Sandia is manufacturing high reliability CMOS ICs with a 0.5 micron CMP technology, as part of the progression to 0.35 micron and smaller scale technologies. To qualify this technology for delivery of high reliability ICs to customers for military, space, and commercial applications, a qualification program has been implemented that includes extensive loop testing. Two vehicles are being used for this qualification, a 256 K bit SRAM and a Microcontroller Core (MCC). Both of these ICs present unique loop testing challenges. This paper describes the methods used to successfully implement I/sub DDQ/ testing for these two types of ICs.