Iddq test pattern generation for scan chain latches and flip-flops

Abstract

A new approach, using Iddq, for testing the bistable elements (latches ad flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking experiment to each bistable element in the circuit while checking their response. Such tests guarantee the detection of all detectable combinational defects inside the bistable elements. We show that this approach is more effective than test generation using the popular pseudo stuck-at-fault model. Our algorithm was implemented by modifying an existing stuck-at combinational test pattern generator. The number of test patterns generated by the new program is comparable to the number of traditional stuck-at-patterns. This shows that our approach is practical for large circuits.