Sequential circuit test generation for IDDQ testing of bridging faults

Abstract

This paper presents a test generation method for sequential circuits assuming IDDQ testing. We consider external bridging faults and internal bridging faults as a target fault. Test generation for external bridging faults consists of three phases as (1) use of weighted random vectors, (2) set of target values on selected signal lines, (3) deterministic test generation for undetected faults. In order to detect internal bridging faults, we use a sequential test generator for stuck-at-faults. Finally experimental results for ISCAS'89 benchmark circuits are given.