{"title":"基于仿真的无缺陷I/sub DDQ/估算方法","authors":"P. Maxwell, J. Rearick","doi":"10.1109/IDDQ.1997.633018","DOIUrl":null,"url":null,"abstract":"This paper presents a switch-level simulation-based method for estimating quiescent current values. The simulator identifier transistors that are in the proper state to experience leakage mechanisms. This information is combined with data about both the size of these transistors and various process parameters in order to calculate the actual I/sub DDQ/ value. SPICE simulation results are also presented on a variety of circuits to both calibrate the simulator, and to demonstrate state, time and sequence dependencies of circuits.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"375 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":"{\"title\":\"A simulation-based method for estimating defect-free I/sub DDQ/\",\"authors\":\"P. Maxwell, J. Rearick\",\"doi\":\"10.1109/IDDQ.1997.633018\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a switch-level simulation-based method for estimating quiescent current values. The simulator identifier transistors that are in the proper state to experience leakage mechanisms. This information is combined with data about both the size of these transistors and various process parameters in order to calculate the actual I/sub DDQ/ value. SPICE simulation results are also presented on a variety of circuits to both calibrate the simulator, and to demonstrate state, time and sequence dependencies of circuits.\",\"PeriodicalId\":429650,\"journal\":{\"name\":\"Digest of Papers IEEE International Workshop on IDDQ Testing\",\"volume\":\"375 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-11-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"23\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers IEEE International Workshop on IDDQ Testing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IDDQ.1997.633018\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers IEEE International Workshop on IDDQ Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IDDQ.1997.633018","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A simulation-based method for estimating defect-free I/sub DDQ/
This paper presents a switch-level simulation-based method for estimating quiescent current values. The simulator identifier transistors that are in the proper state to experience leakage mechanisms. This information is combined with data about both the size of these transistors and various process parameters in order to calculate the actual I/sub DDQ/ value. SPICE simulation results are also presented on a variety of circuits to both calibrate the simulator, and to demonstrate state, time and sequence dependencies of circuits.
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