I/sub DDQ/ testable dynamic PLAs

Abstract

Testing of bridging faults in PLAs by means of voltage testing is expensive. However, same can be done efficiently with I/sub DDQ/ testing. In this article we propose two I/sub DDQ/ testable PLA configurations. In these configurations adjacent precharge lines (and adjacent evaluation lines) are precharged (evaluated) to complementary logic levels. All likely bridging faults in these configurations are tested efficiently by the I/sub DDQ/ test technique. Such a test is independent of the function implemented in a PLA.