An approach for detecting bridging fault-induced delay faults in static CMOS circuits using dynamic power supply current monitoring

Abstract

A new approach for the detection of bridging fault-induced delay faults in static CMOS logic circuits is presented in this paper. It is based upon the transient current that is sourced (or sink) by the power supply (or ground) rail of a primary output gate during a low-to-high (or high-to-low) output transition. We show that the dynamic power supply current (DPSC) can be used to detect delay faults that are due to bridging faults because the DPSC is a function of the parameters and the interconnectivity of the transistors that form the discharge/charge circuits in the gates along the path-under-test. An example of a dynamic power supply current monitoring circuit is also presented. The paper is concluded with an example of the application of the proposed approach for detecting bridging faults in static CMOS logic circuit.