{"title":"I/sub DDQ/可测试动态pla","authors":"M. Sachdev, H. Kerkhoff","doi":"10.1109/IDDQ.1997.633007","DOIUrl":null,"url":null,"abstract":"Testing of bridging faults in PLAs by means of voltage testing is expensive. However, same can be done efficiently with I/sub DDQ/ testing. In this article we propose two I/sub DDQ/ testable PLA configurations. In these configurations adjacent precharge lines (and adjacent evaluation lines) are precharged (evaluated) to complementary logic levels. All likely bridging faults in these configurations are tested efficiently by the I/sub DDQ/ test technique. Such a test is independent of the function implemented in a PLA.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"135 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"I/sub DDQ/ testable dynamic PLAs\",\"authors\":\"M. Sachdev, H. Kerkhoff\",\"doi\":\"10.1109/IDDQ.1997.633007\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Testing of bridging faults in PLAs by means of voltage testing is expensive. However, same can be done efficiently with I/sub DDQ/ testing. In this article we propose two I/sub DDQ/ testable PLA configurations. In these configurations adjacent precharge lines (and adjacent evaluation lines) are precharged (evaluated) to complementary logic levels. All likely bridging faults in these configurations are tested efficiently by the I/sub DDQ/ test technique. Such a test is independent of the function implemented in a PLA.\",\"PeriodicalId\":429650,\"journal\":{\"name\":\"Digest of Papers IEEE International Workshop on IDDQ Testing\",\"volume\":\"135 2\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-11-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers IEEE International Workshop on IDDQ Testing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IDDQ.1997.633007\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers IEEE International Workshop on IDDQ Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IDDQ.1997.633007","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Testing of bridging faults in PLAs by means of voltage testing is expensive. However, same can be done efficiently with I/sub DDQ/ testing. In this article we propose two I/sub DDQ/ testable PLA configurations. In these configurations adjacent precharge lines (and adjacent evaluation lines) are precharged (evaluated) to complementary logic levels. All likely bridging faults in these configurations are tested efficiently by the I/sub DDQ/ test technique. Such a test is independent of the function implemented in a PLA.
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