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Enhanced asymmetry in monolayer graphene geometric diodes 单层石墨烯几何二极管增强的不对称性
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242335
V. Passi, A. Gahoi, M. Lemme
{"title":"Enhanced asymmetry in monolayer graphene geometric diodes","authors":"V. Passi, A. Gahoi, M. Lemme","doi":"10.23919/SNW.2017.8242335","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242335","url":null,"abstract":"Monolayer graphene geometric diodes with neck width of 50 nm exhibit record high current asymmetry of 1.48. Diodes with neck angles of 30° and 45° show no significant change in asymmetry, while a reduction in asymmetry has been observed for a diode with a neck angle of 60°, attributed to the reduction in physical asymmetry of the diode structure.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130234486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 0.9-GHz fully integrated 45% PAE class-Ε power amplifier fabricated using a 0.18-μm CMOS process for LoRa applications 采用 0.18μm CMOS 工艺为 LoRa 应用制造的 0.9-GHz 全集成 45% PAE 等级功率放大器
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242325
Yu-Ting Tseng, Jeng-Rern Yang
{"title":"A 0.9-GHz fully integrated 45% PAE class-Ε power amplifier fabricated using a 0.18-μm CMOS process for LoRa applications","authors":"Yu-Ting Tseng, Jeng-Rern Yang","doi":"10.23919/SNW.2017.8242325","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242325","url":null,"abstract":"A 0.9-GHz fully integrated class-E two-stage power amplifier (PA) for Long Range Wide Area Networks (LoRaWANs) is fabricated using a TSMC 0.18-μm process. This PA employs multiple methods to realize a high efficiency. The injection-locking technique is used to reduce the input driving power. The first stage is utilized as the driver stage to improve the efficiency and decrease the number of inductors used for input and interstage matching. Furthermore, the use of a self-biasing technique could enhance the output power and power added efficiency (PAE). The fully integrated PA can achieve a 19.03-dBm output power for a 50-Ω load with a 45.1% PAE and 29.35-dB power gain.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127856190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Characterictics variability of gate-all-around polycrystalline silicon nanowire transistors with width of 10nm scale 宽度为10nm的栅极全能多晶硅纳米线晶体管的特性变异性
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242283
Ki-Hyun Jang, T. Saraya, M. Kobayashi, N. Sawamoto, A. Ogura, T. Hiramoto
{"title":"Characterictics variability of gate-all-around polycrystalline silicon nanowire transistors with width of 10nm scale","authors":"Ki-Hyun Jang, T. Saraya, M. Kobayashi, N. Sawamoto, A. Ogura, T. Hiramoto","doi":"10.23919/SNW.2017.8242283","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242283","url":null,"abstract":"The polycrystalline silicon (poly-Si) gate-all-around (GAA) nanowire transistors with 10nm scale width were fabricated under precise width control. The nanowire width is 10nm scale. Measured characteristics show smaller threshold voltage and drain current variability than that of previously reported poly-Si nanowire transistors.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115981653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
BEOL compatible WS2 transistors fully fabricated in a 300 mm pilot line BEOL兼容WS2晶体管完全制造在一个300毫米的中导线
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242336
T. Schram, Q. Smets, M. Heyne, B. Graven, E. Kunnen, A. Thiam, K. Devriendt, A. Delabie, D. Lin, D. Chiappe, I. Asselberghs, M. Lux, S. Brus, C. Huyghebaert, S. Sayan, A. Juncker, M. Caymax, I. Radu
{"title":"BEOL compatible WS2 transistors fully fabricated in a 300 mm pilot line","authors":"T. Schram, Q. Smets, M. Heyne, B. Graven, E. Kunnen, A. Thiam, K. Devriendt, A. Delabie, D. Lin, D. Chiappe, I. Asselberghs, M. Lux, S. Brus, C. Huyghebaert, S. Sayan, A. Juncker, M. Caymax, I. Radu","doi":"10.23919/SNW.2017.8242336","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242336","url":null,"abstract":"For the first time, WS2-based transistors have been successfully integrated in a 300 mm pilot line using production tools. The 2D material was deposited using either area selective chemical vapor deposition (CVD) or Atomic Layer Deposition (ALD). No material transfer was required. The major integration challenges are the limited adhesion and the fragility of the few-monolayer 2D material. These issues are avoided by using a sacrificial Al2O3 capping layer and by encapsulating the edges of the 2D material during wet processing. The WS2 channel is contacted with Ti/TiN side contacts and an industry-standard back end of line (BEOL) flow. This novel low-temperature flow is promising for integration of back-gated 2D transistors in the BEOL.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128675425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Fermi level modulation at the interface of graphene and metal 石墨烯与金属界面处的费米能级调制
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242334
Y. Kim, H. Lee, K. Chang, C. Cho, S. K. Lee, B. H. Lee
{"title":"Fermi level modulation at the interface of graphene and metal","authors":"Y. Kim, H. Lee, K. Chang, C. Cho, S. K. Lee, B. H. Lee","doi":"10.23919/SNW.2017.8242334","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242334","url":null,"abstract":"The Fermi level of graphene in contact with the metal contact is a critically important factor for graphene-based device design. Fermi level pinning like behavior at the metal on a graphene can limit the contact resistance reduction and other device operations, especially in high workfunction metal cases. We report that this problem can be substantially alleviated by the hydrogen anneal at high pressure over 20atm.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124672297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of device design parameters on VDSAT and analog performance of TFETs 器件设计参数对tfet VDSAT和模拟性能的影响
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242292
Abhishek Acharya, S. Dasgupta, B. Anand
{"title":"Impact of device design parameters on VDSAT and analog performance of TFETs","authors":"Abhishek Acharya, S. Dasgupta, B. Anand","doi":"10.23919/SNW.2017.8242292","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242292","url":null,"abstract":"We report the impact of device design parameters on the saturation voltages (VDSAT) and thereby on analog performance of the Tunnel FETs (TFET). As the drain bias (VDS) increases, the device initially enters a soft saturation and later into a deep saturation state, both at a constant difference between the gate-drain bias (VGD)· An increase in source (drain) doping decreases (increases) the soft saturation voltage. The short channel lengths degrade the saturation in the TFETs. Agate-drain underlapcauses early onset of the saturation in TFETs, while, a reduction in the nanowire diameter delays the saturation. The output resistance (Ro), transconductance (gm), and intrinsic gain (gm×Ro) increase when the device enters in soft saturation and attain a maxi mum in the deep saturation state. Our work elucidates the physics behind above observations, and provides insights into the device design of the TFETs.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114795904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Negative capacitance tunnel F£Ts: Experimental demonstration of outstanding simultaneous boosting of on-current, transconductance, overdrive, and swing 负电容隧道:同时增强通流、跨导、超速和摆幅的实验证明
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242270
A. Saeidi, F. Jazaeri, I. Stolichnov, G. V. Luong, Q. Zhao, S. Manti, A. Ionescu
{"title":"Negative capacitance tunnel F£Ts: Experimental demonstration of outstanding simultaneous boosting of on-current, transconductance, overdrive, and swing","authors":"A. Saeidi, F. Jazaeri, I. Stolichnov, G. V. Luong, Q. Zhao, S. Manti, A. Ionescu","doi":"10.23919/SNW.2017.8242270","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242270","url":null,"abstract":"This paper demonstrates and experimentally reports the highest ever performance boosting in strained silicon-nanowire homojunction TFETs with negative capacitance, provided by matched PZT capacitors. Outstanding enhancements of Ion, gm, and overdrive are analyzed and explained by most effective reduction of body factor, m < 1, especially for Vg>Vt, which greatly amplify the control on the surface potential TFET, which dictates a highly non-linear BTBT regime. We achieve a full non-hysteretic negative-capacitance switch configuration, suitable for logic applications, and report o«-current increase by a factor of 500x, voltage overdrive of IV, transconductance increase of up to 5× 103x, and subthreshold swing improvement.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128091913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Integrated III-V nanoelectronic devices on Si 硅基集成III-V纳米电子器件
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242267
H. Riel
{"title":"Integrated III-V nanoelectronic devices on Si","authors":"H. Riel","doi":"10.23919/SNW.2017.8242267","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242267","url":null,"abstract":"I will give an overview of our recent work on the integration of III-V semiconductor nano-structures on silicon (Si) for electronic devices. The template-assisted selective epitaxy (TASE) used to monolithically integrate high crystal quality III-V nanostructures on Si is introduced. The challenges and recent progress of the development of nanoscale III-V MOSFETs and Tunnel FETs is discussed and a complementary p-type InAs-Si and η-type InAs-GaSb TFET technology is demonstrated.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126463838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Comparison of parasitic components between LFET and VFET using 3D TCAD 利用三维TCAD比较LFET和VFET的寄生元件
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242312
Minsoo Kim, Hyungwoo Ko, Myounggon Kang, Hyungcheol Shin
{"title":"Comparison of parasitic components between LFET and VFET using 3D TCAD","authors":"Minsoo Kim, Hyungwoo Ko, Myounggon Kang, Hyungcheol Shin","doi":"10.23919/SNW.2017.8242312","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242312","url":null,"abstract":"In this work, we compare parasitic components between lateral nanowire-FET (LFET) and vertical nanowire-FET (VFET) based on ITRS 2015 using 3D Technology Computer-aided Design (TCAD). We compare the parasitic resistances and capacitances in accordance with channel thickness. Further, we analyzed the effects of parasitic components on device performance and proposed the direction of device scaling.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127739784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
2D nanoelectronics: From graphene to silicene and beyond 二维纳米电子学:从石墨烯到硅烯及其他
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242331
D. Akinwande
{"title":"2D nanoelectronics: From graphene to silicene and beyond","authors":"D. Akinwande","doi":"10.23919/SNW.2017.8242331","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242331","url":null,"abstract":"This research work describes progress towards 2D nanoelectronics based on atomic sheets such as graphene, M0S2, black phosphorus, silicene and related materials. These diverse 2D nanomaterials can afford a wide range of device capabilities including low-power transistors, high-speed devices, zero-power switches, and wearable sensors. In addition, silicene, the atomically-thin equivalent of bulk silicon is predicted to be a topological insulator and in conjunction with related Xene sheets, can enable low-energy topological bits as a paradigm-shift for computation.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132807419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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