发布求助
文献互助 智能选刊 最新文献

2017 Silicon Nanoelectronics Workshop (SNW)最新文献

筛选
英文 中文
Uniformity improvement of SiNjc-based resistive switching memory by suppressed internal overshoot current 抑制内部超调电流改善基于sinjc的阻性开关存储器的均匀性
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242276
Min-Hwi Kim, Sungjun Kim, Suhyun Bang, Tae-Hyeon Kim, Dong Keun Lee, Seongjae Cho, Jong-Ho Lee, Byung-Gook Park
{"title":"Uniformity improvement of SiNjc-based resistive switching memory by suppressed internal overshoot current","authors":"Min-Hwi Kim, Sungjun Kim, Suhyun Bang, Tae-Hyeon Kim, Dong Keun Lee, Seongjae Cho, Jong-Ho Lee, Byung-Gook Park","doi":"10.23919/SNW.2017.8242276","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242276","url":null,"abstract":"In this work, we have investigated the effect of thin SiO2 layer on switching variability of SiNx-based RRAM. We found that recessive LRS state generated in set operation results in large reset current and abrupt reset operation. The abrupt reset operation leads to large HRS distribution. To investigate the transient characteristics of switching process in detail, measurement environment is implemented with equivalent circuit and measured current from equipment is separated to capacitive and resistive current element. Consequently, we point the internal overshoot current occurred in set operation as the cause of switching variability and large distribution.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134061939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
More Moore: From device scaling to 3D integration and system-technology co-optimization 摩尔:从设备扩展到3D集成和系统技术协同优化
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242328
N. Collaert
{"title":"More Moore: From device scaling to 3D integration and system-technology co-optimization","authors":"N. Collaert","doi":"10.23919/SNW.2017.8242328","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242328","url":null,"abstract":"In this paper, we will review the current challenges and advancements to continue standard device scaling beyond the 5nm technology node. Apart from the introduction of new materials and device concepts, we will also address the trend towards more heterogeneous systems requiring close interaction between the technology and system optimization.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115656816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of majority logic gate for single-dopant device 单掺杂器件多数逻辑门的设计
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242342
Takahide Ova, T. Shinada
{"title":"Design of majority logic gate for single-dopant device","authors":"Takahide Ova, T. Shinada","doi":"10.23919/SNW.2017.8242342","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242342","url":null,"abstract":"This paper describes a majority logic gate circuit on a “single-dopant” device. The single-dopant device that has been receiving increasing attention in recent years is one of atomic scale solid-state device and can be a practical platform for a single-electron circuit. We here aim to fabricate actual single-dopant majority logic circuits with deterministic doping method. For this, we design a possible circuit on the device and test its operation by Monte Carlo simulation as a first step of this study. As results, we confirmed correct circuit operation and found that the device will have thermal-noise- and device-parameter-fluctuation-harnessing abilities. We believe that we will succeed to fabricate practical the single-dopant majority logic gate circuit in near future.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116618775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Possibility of Si resonant plasma-wave transistor as THz detector 硅谐振等离子体波晶体管作为太赫兹探测器的可能性
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242296
J. Park, Sung-Ho Kim, Kyung Rok Kim
{"title":"Possibility of Si resonant plasma-wave transistor as THz detector","authors":"J. Park, Sung-Ho Kim, Kyung Rok Kim","doi":"10.23919/SNW.2017.8242296","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242296","url":null,"abstract":"In this paper, we show a possibility of Si resonant plasma-wave transistor (R-PWT) as THz detector. Κ the channel mobility of strained Si R-PWT is 400 cm·V<sup>−1·</sup>s<sup>1</sup>, R-PWT can be operated as THz detector when channel length l= 21–28 nm.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128534973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis on self heating effects in nanowire ΓΕΤ considering effective thermal conductivity of BEOL 考虑BEOL有效导热系数的纳米线ΓΕΤ自热效应分析
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242287
Hyunsuk Kim, Dokyun Son, Ilho Myoung, Myounggon Kang, Hyungcheol Shin
{"title":"Analysis on self heating effects in nanowire ΓΕΤ considering effective thermal conductivity of BEOL","authors":"Hyunsuk Kim, Dokyun Son, Ilho Myoung, Myounggon Kang, Hyungcheol Shin","doi":"10.23919/SNW.2017.8242287","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242287","url":null,"abstract":"Accurate evaluation of Self Heating Effects in highly down-scaled devices becomes essential for improved performance and reliability. However, complex structure of BEOL causes analysis of SHEs to be difficult To remove the difficulty, based on Rent's rule to obtain interconnect density function, effective thermal conductivity of BEOL versus metal volume density and average aspect ratio (p) was calculated. With results above, TCAD simulation for SHEs was performed in 5 nm node nanowire FET. As a result, lowered thermal conductivity by complicated structure can bring underestimated SHEs through simulation.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"675 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116105078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High performance Ge pMOSFETs with simultaneous mobility-412 cm2/V-s, EOT −0.5 nm, Ion/Ioff∼105, gate leakage∼10−4 A/cm2 by modulating interfacial layer using oxygen deficient HfOx 通过缺氧HfOx调制界面层，获得了同时迁移率为412 cm2/V-s, EOT为- 0.5 nm，离子/Ioff为- 105，栅极泄漏为- 10−4 A/cm2的高性能Ge pmosfet
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242272
S. Yi, Jiayi Huang, Chia-Wei Hsu, Tzung-Yu Wu, D. Ruan, K. Chang-Liao
{"title":"High performance Ge pMOSFETs with simultaneous mobility-412 cm2/V-s, EOT −0.5 nm, Ion/Ioff∼105, gate leakage∼10−4 A/cm2 by modulating interfacial layer using oxygen deficient HfOx","authors":"S. Yi, Jiayi Huang, Chia-Wei Hsu, Tzung-Yu Wu, D. Ruan, K. Chang-Liao","doi":"10.23919/SNW.2017.8242272","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242272","url":null,"abstract":"A high peak hole mobility of 412 cm<sup>2</sup>/V-sec at Ninv=1.8×10<sup>12</sup> cm<sup>−2</sup>, a very low Jg of ∼10<sup>−4</sup> A/cm<sup>2</sup> at V<inf>g</inf>=V<inf>fb</inf>+1 V and an ultralow EOT of 0.53 nm in Ge pMOSFETs are simultaneously achieved by high-k/0D-HKVGe02 gate stack with suitable treatments. The content of Ge<sup>+1</sup> and Ge<sup>+2</sup> in GeO<inf>x</inf> layer are re-oxidized to higher oxidation state by gettered oxygen, which is captured by OD-HfOx from GeO<inf>x</inf>. The proposed gate stack is promising for Ge MOSFET.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117024615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization of resistive switching memory devices with tunnel barrier 具有隧道势垒的阻性开关存储器件的特性
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242310
Sungjun Kim, Min-Hwi Kim, Tae-Hyeon Kim, Suhyun Bang, Dong Keun Lee, Yao‐Feng Chang, Byung-Gook Park
{"title":"Characterization of resistive switching memory devices with tunnel barrier","authors":"Sungjun Kim, Min-Hwi Kim, Tae-Hyeon Kim, Suhyun Bang, Dong Keun Lee, Yao‐Feng Chang, Byung-Gook Park","doi":"10.23919/SNW.2017.8242310","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242310","url":null,"abstract":"In this work, we study the resistive switching characteristics of two different resistive switching memory devices (SiN<inf>x</inf> and HfO<inf>x</inf>) with SiO<inf>2</inf> tunnel barrier. The switching of the former and the latter is based on the movement of hydrogen ion and oxygen vacancies, respectively. For Cu/SiN<inf>x</inf>/SiO<inf>2</inf>/p<sup>+</sup>-Si device, the operating current is drastically reduced and nonlinearity of LRS is increased compared to without the devices without tunnel barrier. These experiment results demonstrate that the two-types RRAM devices having tunnel barrier is highly suitable for the low-power and high-density memory applications.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132534964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Different pixel patterns of Si-based far infrared bolometers 硅基远红外测热计的不同像素模式
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242321
Feng-Renn Juang, W. Yeh, Wei-Chih Chen, Ming-Feng Chung
{"title":"Different pixel patterns of Si-based far infrared bolometers","authors":"Feng-Renn Juang, W. Yeh, Wei-Chih Chen, Ming-Feng Chung","doi":"10.23919/SNW.2017.8242321","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242321","url":null,"abstract":"Amorphous silicon bolometers with different pixel patterns are investigated for far infrared detection. Devices with floating resonator structure are measured for resistances and temperature coefficient of resistance (TCR) values. The results show normal leg geometry has high TCR (∼ −4%/°C) and moderate resistance. Thus the pixel pattern is suitable for infrared detecting applications.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133062497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Si-on-insulator grating coupler operating at 2 μιη: Device design, fabrication, and characterization 在2 μιη下工作的绝缘体上硅光栅耦合器:器件设计、制造和表征
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242318
Shengqiang Xu, Xin Guo, Yuan Dong, Wei Wang, Hong Wang, X. Gong, Y. Yeo
{"title":"Si-on-insulator grating coupler operating at 2 μιη: Device design, fabrication, and characterization","authors":"Shengqiang Xu, Xin Guo, Yuan Dong, Wei Wang, Hong Wang, X. Gong, Y. Yeo","doi":"10.23919/SNW.2017.8242318","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242318","url":null,"abstract":"Grating coupler based on 220 nm Si-on-insulator (SOI) substrate was designed and optimized for operation at 2 μm wavelength targeting telecommunication application. Decent coupling efficiency of around 18% is achieved, which is consistent with the simulation results and can be employed in 2 μτη-based photonic integrated circuit.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132163816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impacts of diameter and Ge content variation on the performance of Si1−xGex p-channel gate-all-around nanowire transistors 直径和锗含量变化对Si1−xGex p沟道栅全能纳米线晶体管性能的影响
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242285
Xianle Zhang, Xiaoyan Liu, L. Yin, G. Du
{"title":"Impacts of diameter and Ge content variation on the performance of Si1−xGex p-channel gate-all-around nanowire transistors","authors":"Xianle Zhang, Xiaoyan Liu, L. Yin, G. Du","doi":"10.23919/SNW.2017.8242285","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242285","url":null,"abstract":"In this work, the impacts of both nanowire diameter (D<inf>nw</inf>) and Ge content (%) on the performance of Si<inf>1−x</inf>Ge<inf>x</inf> Gate-All-Around nanowire p-channel FETs (GAA pNWTs) are investigated. The variations in SiGe GAA pNWTs induced by D<inf>nw</inf> variation, Ge content variation and some stochastic process variations including of random dopants fluctuation (RDF), gate edge roughness (GER), and metal gate granularity (MGG) are also simulated.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"250 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122201156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信