{"title":"硅基集成III-V纳米电子器件","authors":"H. Riel","doi":"10.23919/SNW.2017.8242267","DOIUrl":null,"url":null,"abstract":"I will give an overview of our recent work on the integration of III-V semiconductor nano-structures on silicon (Si) for electronic devices. The template-assisted selective epitaxy (TASE) used to monolithically integrate high crystal quality III-V nanostructures on Si is introduced. The challenges and recent progress of the development of nanoscale III-V MOSFETs and Tunnel FETs is discussed and a complementary p-type InAs-Si and η-type InAs-GaSb TFET technology is demonstrated.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Integrated III-V nanoelectronic devices on Si\",\"authors\":\"H. Riel\",\"doi\":\"10.23919/SNW.2017.8242267\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"I will give an overview of our recent work on the integration of III-V semiconductor nano-structures on silicon (Si) for electronic devices. The template-assisted selective epitaxy (TASE) used to monolithically integrate high crystal quality III-V nanostructures on Si is introduced. The challenges and recent progress of the development of nanoscale III-V MOSFETs and Tunnel FETs is discussed and a complementary p-type InAs-Si and η-type InAs-GaSb TFET technology is demonstrated.\",\"PeriodicalId\":424135,\"journal\":{\"name\":\"2017 Silicon Nanoelectronics Workshop (SNW)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Silicon Nanoelectronics Workshop (SNW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/SNW.2017.8242267\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Silicon Nanoelectronics Workshop (SNW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/SNW.2017.8242267","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
I will give an overview of our recent work on the integration of III-V semiconductor nano-structures on silicon (Si) for electronic devices. The template-assisted selective epitaxy (TASE) used to monolithically integrate high crystal quality III-V nanostructures on Si is introduced. The challenges and recent progress of the development of nanoscale III-V MOSFETs and Tunnel FETs is discussed and a complementary p-type InAs-Si and η-type InAs-GaSb TFET technology is demonstrated.
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