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2017 Silicon Nanoelectronics Workshop (SNW)最新文献

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Harmonie innovatios in semiconductor devices and computer architectures toward post “Moore-era” 面向后“摩尔时代”的半导体器件和计算机架构的和谐创新
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242327
Y. Hayashi
{"title":"Harmonie innovatios in semiconductor devices and computer architectures toward post “Moore-era”","authors":"Y. Hayashi","doi":"10.23919/SNW.2017.8242327","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242327","url":null,"abstract":"Simple 2D scaling of semiconductor devices by “Moore's law” will not work well soon to improve the performances and power efficiencies due to tight physical directional limits. System integrations, however, might continue to advance further by 3D structural evolutions either in monolithic on-chip integrations or heterogeneous off-chip stacks. Accelerated implementations of new architectures and new functional materials would be key factors, especially to execute machine learnings more efficiently for ΑΙ-based smart applications. Just now, we have established SDRJ (The System Device Roadmap Committee of Japan, https://www.sdrj.jp/) in JSAP collaborated with IEEE IRDS (International Roadmap for Devices and Systems, http://irds.ieee.org/) to discuss the roadmaps internationally toward the year of 2030.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127880551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Gated-thyristor DRAM cell with pillar channel structure 具有柱状通道结构的门控晶闸管DRAM单元
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242302
Hyungjin Kim, M. Kwon, Myung-Hyun Baek, Sungmin Hwang, Sihyun Kim, Taejin Jang, Jeong-Jun Lee, Hyun-Min Kim, Kitae Lee, Byung-Gook Park
{"title":"Gated-thyristor DRAM cell with pillar channel structure","authors":"Hyungjin Kim, M. Kwon, Myung-Hyun Baek, Sungmin Hwang, Sihyun Kim, Taejin Jang, Jeong-Jun Lee, Hyun-Min Kim, Kitae Lee, Byung-Gook Park","doi":"10.23919/SNW.2017.8242302","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242302","url":null,"abstract":"In this work, a DRAM cell based on gated-thyristor having pillar channel and sidewall gate is proposed and investigated through device simulation study. Stored electrons in the base region make a difference in read current lowering potential barrier. It has a fast writing speed under 10 ns because of its mechanism based on thermal injection and highly scalable structure because of self-connected word line.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117128635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis on extension region in nanowire FET considering RC delay and electrical characteristics 考虑RC延迟和电学特性的纳米线场效应管扩展区分析
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242288
Jongsu Kim, Changbeom Woo, Myounggon Kang, Hyungcheol Shin
{"title":"Analysis on extension region in nanowire FET considering RC delay and electrical characteristics","authors":"Jongsu Kim, Changbeom Woo, Myounggon Kang, Hyungcheol Shin","doi":"10.23919/SNW.2017.8242288","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242288","url":null,"abstract":"Device characteristics in the operating region, subthreshold region, and OFF region were analyzed to propose optimum design guideline for nanowire FET. First, the research was focused on the structure of extension region in perspective of RC delay. Also, Subthreshold Swing (SS) and Gate Induced Drain Leakage (GIDL) were investigated because these characteristics are greatly affected by the structure of the extension region. Therefore, by considering all characteristics in three regions of the device, it was found that the best characteristics were shown when the extension length was 6 nm without an overlap or with slight underlap.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115699829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
GeSn N-FinFETs and NiGeSn contact formation by phosphorus implant 磷植入形成的GeSn n - finfet与NiGeSn触点
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242315
Y. Chuang, Hsien-chih Huang, Jiun-Yun Li
{"title":"GeSn N-FinFETs and NiGeSn contact formation by phosphorus implant","authors":"Y. Chuang, Hsien-chih Huang, Jiun-Yun Li","doi":"10.23919/SNW.2017.8242315","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242315","url":null,"abstract":"We report n-FinFETs with a high drive current of 108 Aim and the best SS of 138 mV/dec. A higher drive current was achieved by the reduction of series S/D resistance. NiGeSn/n<sup>+</sup>-GeSn contact formation was done by rapid thermal annealing below 400 °C. Contact resistivity was characterized by circular transmission line model. The contact resistance decreases with the carrier concentration or Sn fraction in GeSn films with the lowest contact resistivity of 3.8×10<sup>−8</sup> Ω-cm<sup>2</sup>.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122141245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Theoretical analysis of quasi-ballistic hole transport in Ge and Si nanowires focusing on energy relaxation process 基于能量松弛过程的锗和硅纳米线准弹道空穴输运理论分析
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242284
Hajime Tanaka, J. Suda, T. Kimoto
{"title":"Theoretical analysis of quasi-ballistic hole transport in Ge and Si nanowires focusing on energy relaxation process","authors":"Hajime Tanaka, J. Suda, T. Kimoto","doi":"10.23919/SNW.2017.8242284","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242284","url":null,"abstract":"The quasi-ballistic hole transport capabilities of Ge and Si NWs were calculated using atomistic electron-phonon coupling and Boltzmann transport equation. Analyzing the forward and backward current fluxes, it was shown that the positive impact of high mobility of Ge is canceled by its slower energy relaxation, which results in comparable transmission coefficients and current transport capabilities between Ge and Si NWs.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123570993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
RRAM-based pattern recognition system with locally inhibited post-neurons 基于局部抑制后神经元的随机存储器模式识别系统
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242340
Zheng Zhou, Peng Huang, Yuning Jiang, Zhe Chen, Chen Liu, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang
{"title":"RRAM-based pattern recognition system with locally inhibited post-neurons","authors":"Zheng Zhou, Peng Huang, Yuning Jiang, Zhe Chen, Chen Liu, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang","doi":"10.23919/SNW.2017.8242340","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242340","url":null,"abstract":"A novel RRAM-based pattern recognition system with locally inhibited post-neurons is developed. The system is able to learn the whole MNIST training set (60,000 patterns). By using the system, the same post-neuron is fired by the similar patterns in the same training class, which causes the reduction of hardware cost. With the locally inhibited post-neuron, the system can achieve more than 90.73% recognition accuracy.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133963804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel vertical tunnel FET of band-to-band tunneling aligned with gate electric field with averaged SS of 28 mV/decade 一种新型垂直隧道场效应管，带对带隧道与栅极电场排列，平均SS为28 mV/ 10年
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242291
Pao-Chuan Shih, Hsien-chih Huang, Chien-An Wang, Jiun-Yun Li
{"title":"A novel vertical tunnel FET of band-to-band tunneling aligned with gate electric field with averaged SS of 28 mV/decade","authors":"Pao-Chuan Shih, Hsien-chih Huang, Chien-An Wang, Jiun-Yun Li","doi":"10.23919/SNW.2017.8242291","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242291","url":null,"abstract":"We propose a novel vertical tunnel FET of band-to-band tunneling aligned with the gate electric field. Simulation results show high drive current and extremely sharp subthreshold swing due to excellent gate control over the tunnel junction. OFF state leakage via source-to-drain tunneling is much suppressed by the spacer layer between the source and drain layers. Furthermore, this device is fully compatible to VLSI technology.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133414396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Implementation of inhibitory operation in neuromorphic system 神经形态系统抑制操作的实施
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242323
Jeong-Jun Lee, M. Kwon, Hyungjin Kim, Sungmin Hwang, Byung-Gook Park
{"title":"Implementation of inhibitory operation in neuromorphic system","authors":"Jeong-Jun Lee, M. Kwon, Hyungjin Kim, Sungmin Hwang, Byung-Gook Park","doi":"10.23919/SNW.2017.8242323","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242323","url":null,"abstract":"An inhibition part of synapse-neuron connection is indispensable in a neuromorphic system for hardware implementation of artificial intelligence. First, when the system operates with the winner takes all method, a lateral inhibition is required to permit one neuron firing, thereby preventing other neurons from firing. In addition, in order to implement the negative weight, an inhibition part, which is the role of subtracting the signal, must be accompanied. Therefore, in this paper, the structure of a simple inhibition part for lateral inhibition and negative weight is presented and it is verified by simulation.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122188552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of two divided component of NBTI framework using TCAD simulation 利用TCAD仿真分析NBTI框架的两分分量
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242311
Shinkeun Kim, Youngsoo Seo, Dokyun Son, Myounggon Kang, Hyungcheol Shin
{"title":"Analysis of two divided component of NBTI framework using TCAD simulation","authors":"Shinkeun Kim, Youngsoo Seo, Dokyun Son, Myounggon Kang, Hyungcheol Shin","doi":"10.23919/SNW.2017.8242311","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242311","url":null,"abstract":"In this paper, the two Negative Bias Temperature Instability (NBTI) framework components are divided with interface trap generation (Δ Vit) and hole trapping in pre-existing defects (Δ Vht). The threshold voltage shift (ΔVT) contribution is verified by two divided components and studied independently. The impact of inter layer (IL) thickness is simulated under NBTI stress using technology computer-aided design (TCAD) software.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127090288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new operation scheme to obtain 3-bit capacity per cell in HfO2 based RRAM with high uniformity 提出了一种在高均匀性的HfO2 RRAM中获得每单元3位容量的新操作方案
2017 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242308
D. Zhu, Xiangxiang Ding, Peng Huang, Zheng Zhou, Xiaolu Ma, Lifeng Liu, Jinfeng Kang, Xing Zhang
{"title":"A new operation scheme to obtain 3-bit capacity per cell in HfO2 based RRAM with high uniformity","authors":"D. Zhu, Xiangxiang Ding, Peng Huang, Zheng Zhou, Xiaolu Ma, Lifeng Liu, Jinfeng Kang, Xing Zhang","doi":"10.23919/SNW.2017.8242308","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242308","url":null,"abstract":"In this work, HfO2 based resistive random access memory (RRAM) is fabricated and 3-bit storage capacity per cell is demonstrated under both DC and AC mode. In the AC mode, a new operation scheme of balancing set process and reset process is proposed to improve the resistance distribution uniformity (relative standard deviation about 21.1%). The relatives between set and reset parameters are also discussed and a simple model is used to explain these results.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116957269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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