Analysis on extension region in nanowire FET considering RC delay and electrical characteristics

Abstract

Device characteristics in the operating region, subthreshold region, and OFF region were analyzed to propose optimum design guideline for nanowire FET. First, the research was focused on the structure of extension region in perspective of RC delay. Also, Subthreshold Swing (SS) and Gate Induced Drain Leakage (GIDL) were investigated because these characteristics are greatly affected by the structure of the extension region. Therefore, by considering all characteristics in three regions of the device, it was found that the best characteristics were shown when the extension length was 6 nm without an overlap or with slight underlap.