Hyungjin Kim, M. Kwon, Myung-Hyun Baek, Sungmin Hwang, Sihyun Kim, Taejin Jang, Jeong-Jun Lee, Hyun-Min Kim, Kitae Lee, Byung-Gook Park
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Gated-thyristor DRAM cell with pillar channel structure
In this work, a DRAM cell based on gated-thyristor having pillar channel and sidewall gate is proposed and investigated through device simulation study. Stored electrons in the base region make a difference in read current lowering potential barrier. It has a fast writing speed under 10 ns because of its mechanism based on thermal injection and highly scalable structure because of self-connected word line.
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