A 0.9-GHz fully integrated 45% PAE class-Ε power amplifier fabricated using a 0.18-μm CMOS process for LoRa applications

Yu-Ting Tseng, Jeng-Rern Yang
{"title":"A 0.9-GHz fully integrated 45% PAE class-Ε power amplifier fabricated using a 0.18-μm CMOS process for LoRa applications","authors":"Yu-Ting Tseng, Jeng-Rern Yang","doi":"10.23919/SNW.2017.8242325","DOIUrl":null,"url":null,"abstract":"A 0.9-GHz fully integrated class-E two-stage power amplifier (PA) for Long Range Wide Area Networks (LoRaWANs) is fabricated using a TSMC 0.18-μm process. This PA employs multiple methods to realize a high efficiency. The injection-locking technique is used to reduce the input driving power. The first stage is utilized as the driver stage to improve the efficiency and decrease the number of inductors used for input and interstage matching. Furthermore, the use of a self-biasing technique could enhance the output power and power added efficiency (PAE). The fully integrated PA can achieve a 19.03-dBm output power for a 50-Ω load with a 45.1% PAE and 29.35-dB power gain.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Silicon Nanoelectronics Workshop (SNW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/SNW.2017.8242325","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

A 0.9-GHz fully integrated class-E two-stage power amplifier (PA) for Long Range Wide Area Networks (LoRaWANs) is fabricated using a TSMC 0.18-μm process. This PA employs multiple methods to realize a high efficiency. The injection-locking technique is used to reduce the input driving power. The first stage is utilized as the driver stage to improve the efficiency and decrease the number of inductors used for input and interstage matching. Furthermore, the use of a self-biasing technique could enhance the output power and power added efficiency (PAE). The fully integrated PA can achieve a 19.03-dBm output power for a 50-Ω load with a 45.1% PAE and 29.35-dB power gain.
采用 0.18μm CMOS 工艺为 LoRa 应用制造的 0.9-GHz 全集成 45% PAE 等级功率放大器
采用台积电 0.18-μm 工艺制造了一款用于长距离广域网 (LoRaWAN) 的 0.9-GHz 全集成 E 类两级功率放大器 (PA)。该功率放大器采用多种方法实现高效率。注入锁定技术用于降低输入驱动功率。第一级被用作驱动级,以提高效率并减少用于输入和级间匹配的电感器数量。此外,自偏压技术的使用可提高输出功率和功率附加效率(PAE)。全集成功率放大器在 50Ω 负载下的输出功率可达 19.03dBm,功率附加效率为 45.1%,功率增益为 29.35dB。
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