BEOL兼容WS2晶体管完全制造在一个300毫米的中导线

T. Schram, Q. Smets, M. Heyne, B. Graven, E. Kunnen, A. Thiam, K. Devriendt, A. Delabie, D. Lin, D. Chiappe, I. Asselberghs, M. Lux, S. Brus, C. Huyghebaert, S. Sayan, A. Juncker, M. Caymax, I. Radu
{"title":"BEOL兼容WS2晶体管完全制造在一个300毫米的中导线","authors":"T. Schram, Q. Smets, M. Heyne, B. Graven, E. Kunnen, A. Thiam, K. Devriendt, A. Delabie, D. Lin, D. Chiappe, I. Asselberghs, M. Lux, S. Brus, C. Huyghebaert, S. Sayan, A. Juncker, M. Caymax, I. Radu","doi":"10.23919/SNW.2017.8242336","DOIUrl":null,"url":null,"abstract":"For the first time, WS2-based transistors have been successfully integrated in a 300 mm pilot line using production tools. The 2D material was deposited using either area selective chemical vapor deposition (CVD) or Atomic Layer Deposition (ALD). No material transfer was required. The major integration challenges are the limited adhesion and the fragility of the few-monolayer 2D material. These issues are avoided by using a sacrificial Al2O3 capping layer and by encapsulating the edges of the 2D material during wet processing. The WS2 channel is contacted with Ti/TiN side contacts and an industry-standard back end of line (BEOL) flow. This novel low-temperature flow is promising for integration of back-gated 2D transistors in the BEOL.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"BEOL compatible WS2 transistors fully fabricated in a 300 mm pilot line\",\"authors\":\"T. Schram, Q. Smets, M. Heyne, B. Graven, E. Kunnen, A. Thiam, K. Devriendt, A. Delabie, D. Lin, D. Chiappe, I. Asselberghs, M. Lux, S. Brus, C. Huyghebaert, S. Sayan, A. Juncker, M. Caymax, I. Radu\",\"doi\":\"10.23919/SNW.2017.8242336\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For the first time, WS2-based transistors have been successfully integrated in a 300 mm pilot line using production tools. The 2D material was deposited using either area selective chemical vapor deposition (CVD) or Atomic Layer Deposition (ALD). No material transfer was required. The major integration challenges are the limited adhesion and the fragility of the few-monolayer 2D material. These issues are avoided by using a sacrificial Al2O3 capping layer and by encapsulating the edges of the 2D material during wet processing. The WS2 channel is contacted with Ti/TiN side contacts and an industry-standard back end of line (BEOL) flow. This novel low-temperature flow is promising for integration of back-gated 2D transistors in the BEOL.\",\"PeriodicalId\":424135,\"journal\":{\"name\":\"2017 Silicon Nanoelectronics Workshop (SNW)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Silicon Nanoelectronics Workshop (SNW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/SNW.2017.8242336\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Silicon Nanoelectronics Workshop (SNW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/SNW.2017.8242336","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

摘要

基于ws2的晶体管首次使用生产工具成功集成在300mm中试线上。采用区域选择性化学气相沉积(CVD)或原子层沉积(ALD)沉积二维材料。不需要材料转移。主要的集成挑战是有限的粘附性和少数单层二维材料的脆弱性。通过在湿法加工过程中使用牺牲的Al2O3封盖层和封装2D材料的边缘,可以避免这些问题。WS2通道与Ti/TiN侧触点和行业标准的后端线(BEOL)流接触。这种新颖的低温流为在BEOL中集成背控二维晶体管提供了前景。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
BEOL compatible WS2 transistors fully fabricated in a 300 mm pilot line
For the first time, WS2-based transistors have been successfully integrated in a 300 mm pilot line using production tools. The 2D material was deposited using either area selective chemical vapor deposition (CVD) or Atomic Layer Deposition (ALD). No material transfer was required. The major integration challenges are the limited adhesion and the fragility of the few-monolayer 2D material. These issues are avoided by using a sacrificial Al2O3 capping layer and by encapsulating the edges of the 2D material during wet processing. The WS2 channel is contacted with Ti/TiN side contacts and an industry-standard back end of line (BEOL) flow. This novel low-temperature flow is promising for integration of back-gated 2D transistors in the BEOL.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信