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2016 IEEE International Nanoelectronics Conference (INEC)最新文献

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High holding voltage SCR with shunt-transistors to avoid the latch-up effect 高保持电压可控硅与分流晶体管，以避免闭锁效应
2016 IEEE International Nanoelectronics Conference (INEC) Pub Date : 2016-05-09 DOI: 10.1109/INEC.2016.7589357
Huang Xiaozong, Liu Zhiwei, L. Fan, Cheng Hui, J. Liou
{"title":"High holding voltage SCR with shunt-transistors to avoid the latch-up effect","authors":"Huang Xiaozong, Liu Zhiwei, L. Fan, Cheng Hui, J. Liou","doi":"10.1109/INEC.2016.7589357","DOIUrl":"https://doi.org/10.1109/INEC.2016.7589357","url":null,"abstract":"A device for electrostatic discharge MDSCR (Modified Dual-SCR) with high holding voltage (HHVDDSCR) is presented in this paper. Several diffusion regions are inserted in the discharge current path to reduce the feedback effect with the shunt-transistors. Compared to the traditional methodologies to increase the holding voltage, the HHVMLDSCR can achieve higher holding voltage performance without any additional area cost and robustness of the device verified in in a 0.18μm CMOS process. The operational mechanisms of the device is discussed, and the effect of inserted P+/N+ diffusion regions on the SCR is analyzed with TLPI-V characteristics.","PeriodicalId":416565,"journal":{"name":"2016 IEEE International Nanoelectronics Conference (INEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134115932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modeling of 0.18 μm NMOSFETs for TID effect 用于TID效应的0.18 μm nmosfet建模
2016 IEEE International Nanoelectronics Conference (INEC) Pub Date : 2016-05-09 DOI: 10.1109/INEC.2016.7589287
Tiehu Li, Yintang Yang, Tao Liu
{"title":"Modeling of 0.18 μm NMOSFETs for TID effect","authors":"Tiehu Li, Yintang Yang, Tao Liu","doi":"10.1109/INEC.2016.7589287","DOIUrl":"https://doi.org/10.1109/INEC.2016.7589287","url":null,"abstract":"Based on total ionizing dose (TID) irradiation tests, transistor irradiation models for both strip-gate and edgeless structures were created. Only 5% model error was incurred in off state or subthreshold region and a lower 1% error in linear region or saturation region. Edgeless structure was demonstrated to be radiation hardened. The effectiveness of proposed models was validated by application to a reference circuit simulation.","PeriodicalId":416565,"journal":{"name":"2016 IEEE International Nanoelectronics Conference (INEC)","volume":"8 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134171990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Improved patch-clamp amplifier using software-based high-frequency boost 基于软件的高频升压改进膜片钳放大器
2016 IEEE International Nanoelectronics Conference (INEC) Pub Date : 2016-05-09 DOI: 10.1109/INEC.2016.7589385
Jie Luo, Zhenhua Song, A. Qu
{"title":"Improved patch-clamp amplifier using software-based high-frequency boost","authors":"Jie Luo, Zhenhua Song, A. Qu","doi":"10.1109/INEC.2016.7589385","DOIUrl":"https://doi.org/10.1109/INEC.2016.7589385","url":null,"abstract":"The large feedback resistors in the headstage of the patch-clamp amplifier lower the recording bandwidth to less than 100 Hz. A software-based high-frequency boost (SHB) was introduced in this paper. The algorithm consisted of two parts: 1) headstage dynamic characteristic identification using 4SID method; 2) bandwidth compensation using zero-pole matching. Both time and frequency domain analysis demonstrated SHB should be a satisfied alternative to the traditional high-frequency boost circuit.","PeriodicalId":416565,"journal":{"name":"2016 IEEE International Nanoelectronics Conference (INEC)","volume":"309 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122973113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel dual direction SCR device for advanced nanoscale CMOS process 一种用于先进纳米级CMOS工艺的新型双向可控硅器件
2016 IEEE International Nanoelectronics Conference (INEC) Pub Date : 2016-05-09 DOI: 10.1109/INEC.2016.7589447
Du Feibo, Liu Ji-zhi, Liu Zhiwei, Qian Lingli, Chen Chen
{"title":"A novel dual direction SCR device for advanced nanoscale CMOS process","authors":"Du Feibo, Liu Ji-zhi, Liu Zhiwei, Qian Lingli, Chen Chen","doi":"10.1109/INEC.2016.7589447","DOIUrl":"https://doi.org/10.1109/INEC.2016.7589447","url":null,"abstract":"This paper presents a novel dual direction silicon-controlled rectifier device for electrostatic discharge (ESD) protection. An additional p-type ESD implantation layer was added to realize the proposed device (EDDSCR), playing the role of P-well in the traditional Dual SCR. A modified EDDSCR (MEDDSCR) with lower trigger voltage by inserted a PMOS is also proposed. TCAD simulation indicates that the proposed device has advantages of low trigger voltage, low conduction resistance, and good latch-up immunity, making it very suitable for ESD protection in I/O and Core circuits of 28 nm CMOS process.","PeriodicalId":416565,"journal":{"name":"2016 IEEE International Nanoelectronics Conference (INEC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123005012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A semi-digital delay-locked loop with infinite phase capture range and excellent linearity 半数字锁相环，具有无限相位捕获范围和良好的线性
2016 IEEE International Nanoelectronics Conference (INEC) Pub Date : 2016-05-09 DOI: 10.1109/INEC.2016.7589271
Yi Ding, Xi Duan, Jiandong Zang, Xianjie Wan, Jun Liu, Weidong Yang
{"title":"A semi-digital delay-locked loop with infinite phase capture range and excellent linearity","authors":"Yi Ding, Xi Duan, Jiandong Zang, Xianjie Wan, Jun Liu, Weidong Yang","doi":"10.1109/INEC.2016.7589271","DOIUrl":"https://doi.org/10.1109/INEC.2016.7589271","url":null,"abstract":"This paper describes a high linearity and high resolution semi-digital delay-locked loop (DLL) architecture using a multiphase generator and a phase rotator to get infinite phase capture range, in the meanwhile using current interpolation to obtain high linearity and high resolution. The multiphase generator generates quadrature clocks for the phase rotator instead of a delay line. Thus the phase capture range will change with the changing of input clock rate. An infinite phase capture range can be achieved. The current interpolation is used to eliminate the drawbacks of quadrature phase mixing. The results of simulation show that this semi-digital DLL architecture exhibits 7 picosecond resolution and high linearity at 1.25GHz.","PeriodicalId":416565,"journal":{"name":"2016 IEEE International Nanoelectronics Conference (INEC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127728029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Radiation hardened by design techniques to mitigating P-hit single event transient 通过设计技术增强辐射，以减轻p击单事件瞬态
2016 IEEE International Nanoelectronics Conference (INEC) Pub Date : 2016-05-09 DOI: 10.1109/INEC.2016.7589255
Yihua Chen, M. Tang, Shaoan Yan, Wanli Zhang, Youlin Yin
{"title":"Radiation hardened by design techniques to mitigating P-hit single event transient","authors":"Yihua Chen, M. Tang, Shaoan Yan, Wanli Zhang, Youlin Yin","doi":"10.1109/INEC.2016.7589255","DOIUrl":"https://doi.org/10.1109/INEC.2016.7589255","url":null,"abstract":"As technologies scale down in size, the single event effect has become a universal phenomenon. In this work, a new radiation hardened by design (RHBD) technique has been proposed to mitigating P-hit single event transient. This method is named here as the 3 transistor common drain (3TCD) method. With simulations of the inverter chain using a three-dimensional (3D) technology computer-aided design (TCAD) simulation tool, it has been found that this new 3TCD method has an obvious effect on the p-channel metal-oxide semiconductor field-effect transistor (PMOS FET) by mitigating single event transient (SET) pulse widths (WSET).","PeriodicalId":416565,"journal":{"name":"2016 IEEE International Nanoelectronics Conference (INEC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128930329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On-chip ESD protection design for HV integrated circuits 高压集成电路的片上ESD保护设计
2016 IEEE International Nanoelectronics Conference (INEC) Pub Date : 2016-05-09 DOI: 10.1109/INEC.2016.7589428
M. Ker
{"title":"On-chip ESD protection design for HV integrated circuits","authors":"M. Ker","doi":"10.1109/INEC.2016.7589428","DOIUrl":"https://doi.org/10.1109/INEC.2016.7589428","url":null,"abstract":"Electrostatic discharge (ESD) protection has been an important reliability issue to CMOS integrated circuits, especially in high-voltage (HV) applications. In this invited talk, a brief overview on ESD protection designs for HV integrated circuits is presented. The useful and safe solutions are highlighted for real applications in HV IC products.","PeriodicalId":416565,"journal":{"name":"2016 IEEE International Nanoelectronics Conference (INEC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117009323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multifunctional perovskite photovoltachromic supercapacitor 多功能钙钛矿光致发光超级电容器
2016 IEEE International Nanoelectronics Conference (INEC) Pub Date : 2016-05-09 DOI: 10.1109/INEC.2016.7589411
F. Zhou, Yuda Zhao, Xinpeng Shen, Y. Chai, Qianli Ma
{"title":"Multifunctional perovskite photovoltachromic supercapacitor","authors":"F. Zhou, Yuda Zhao, Xinpeng Shen, Y. Chai, Qianli Ma","doi":"10.1109/INEC.2016.7589411","DOIUrl":"https://doi.org/10.1109/INEC.2016.7589411","url":null,"abstract":"New type of photovoltachromic supercapacitor integrating perovskite solar cell and electrochromic supercapacitor are demonstrated. This photovoltachromic supercapacitor provides a seamless integration of energy harvesting and storage device, accompanying with the change in colored states from semitransparent to blue, which prevents the perovskite solar cell from long-time light exposure and enhance its photo-stability.","PeriodicalId":416565,"journal":{"name":"2016 IEEE International Nanoelectronics Conference (INEC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116662924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A high voltage narrow pulse generator in nanometre CMOS process 一种纳米CMOS制程高压窄脉冲发生器
2016 IEEE International Nanoelectronics Conference (INEC) Pub Date : 2016-05-09 DOI: 10.1109/INEC.2016.7589262
Rongbin Hu, Lei Zhang
{"title":"A high voltage narrow pulse generator in nanometre CMOS process","authors":"Rongbin Hu, Lei Zhang","doi":"10.1109/INEC.2016.7589262","DOIUrl":"https://doi.org/10.1109/INEC.2016.7589262","url":null,"abstract":"A high voltage narrow pulse generating circuit (HNPG) in 90nm CMOS process is introduced which can produce a narrow pulse with amplitude of twice the level of the power supply and can be used to turn on a NMOS transistor completely in a short time in the low power supply environment of 90nm CMOS process. The circuit, which is applied for a patent with the application number 201510243084.6 [1], solves the problem that under the low power level of the nano-metre CMOS process chips, a NMOS transistor can't be turned on completely. The sampling rate of the tracking and holding circuit which employ the HNPG is improved from 700Msps to 1.25Gsps and other performances are also enhanced, with only a little punishment of chip area and power consumption.","PeriodicalId":416565,"journal":{"name":"2016 IEEE International Nanoelectronics Conference (INEC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116804392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Sol-gel strontium titanate nickelate thin films for flexible nonvolatile memory applications 柔性非易失性存储器用钛酸锶镍酸盐溶胶-凝胶薄膜
2016 IEEE International Nanoelectronics Conference (INEC) Pub Date : 2016-05-09 DOI: 10.1109/INEC.2016.7589406
Ke-Jing Lee, Yu‐Chi Chang, Cheng-Jung Lee, Li-Wen Wang, Yeong-Her Wang, D. Chou
{"title":"Sol-gel strontium titanate nickelate thin films for flexible nonvolatile memory applications","authors":"Ke-Jing Lee, Yu‐Chi Chang, Cheng-Jung Lee, Li-Wen Wang, Yeong-Her Wang, D. Chou","doi":"10.1109/INEC.2016.7589406","DOIUrl":"https://doi.org/10.1109/INEC.2016.7589406","url":null,"abstract":"Bipolar resistive switching random access memory (RRAM) devices on a plastic substrate are investigated. Strontium titanate nickelate (STN) thin film prepared by sol-gel method served as insulator on an Al/STN/ITO/PET structure. The STN-based flexible RRAM shows a high ON/OFF resistance ratio (≥ 105) and a retention ability of over 105 s. The characteristics of Ni in the STO thin films demonstrate that spin casting without doping other elements or any complex processes can be used to fabricate thin films with higher density of oxygen vacancies, less particles, and smoother surface. In addition, the fabricated devices on a flexible plastic substrate exhibit excellent durability upon repeated bending tests, demonstrating the potential for flexible and low-cost memory applications.","PeriodicalId":416565,"journal":{"name":"2016 IEEE International Nanoelectronics Conference (INEC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125596796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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