Huang Xiaozong, Liu Zhiwei, L. Fan, Cheng Hui, J. Liou
{"title":"High holding voltage SCR with shunt-transistors to avoid the latch-up effect","authors":"Huang Xiaozong, Liu Zhiwei, L. Fan, Cheng Hui, J. Liou","doi":"10.1109/INEC.2016.7589357","DOIUrl":null,"url":null,"abstract":"A device for electrostatic discharge MDSCR (Modified Dual-SCR) with high holding voltage (HHVDDSCR) is presented in this paper. Several diffusion regions are inserted in the discharge current path to reduce the feedback effect with the shunt-transistors. Compared to the traditional methodologies to increase the holding voltage, the HHVMLDSCR can achieve higher holding voltage performance without any additional area cost and robustness of the device verified in in a 0.18μm CMOS process. The operational mechanisms of the device is discussed, and the effect of inserted P+/N+ diffusion regions on the SCR is analyzed with TLPI-V characteristics.","PeriodicalId":416565,"journal":{"name":"2016 IEEE International Nanoelectronics Conference (INEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Nanoelectronics Conference (INEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INEC.2016.7589357","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A device for electrostatic discharge MDSCR (Modified Dual-SCR) with high holding voltage (HHVDDSCR) is presented in this paper. Several diffusion regions are inserted in the discharge current path to reduce the feedback effect with the shunt-transistors. Compared to the traditional methodologies to increase the holding voltage, the HHVMLDSCR can achieve higher holding voltage performance without any additional area cost and robustness of the device verified in in a 0.18μm CMOS process. The operational mechanisms of the device is discussed, and the effect of inserted P+/N+ diffusion regions on the SCR is analyzed with TLPI-V characteristics.