Du Feibo, Liu Ji-zhi, Liu Zhiwei, Qian Lingli, Chen Chen
{"title":"A novel dual direction SCR device for advanced nanoscale CMOS process","authors":"Du Feibo, Liu Ji-zhi, Liu Zhiwei, Qian Lingli, Chen Chen","doi":"10.1109/INEC.2016.7589447","DOIUrl":null,"url":null,"abstract":"This paper presents a novel dual direction silicon-controlled rectifier device for electrostatic discharge (ESD) protection. An additional p-type ESD implantation layer was added to realize the proposed device (EDDSCR), playing the role of P-well in the traditional Dual SCR. A modified EDDSCR (MEDDSCR) with lower trigger voltage by inserted a PMOS is also proposed. TCAD simulation indicates that the proposed device has advantages of low trigger voltage, low conduction resistance, and good latch-up immunity, making it very suitable for ESD protection in I/O and Core circuits of 28 nm CMOS process.","PeriodicalId":416565,"journal":{"name":"2016 IEEE International Nanoelectronics Conference (INEC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Nanoelectronics Conference (INEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INEC.2016.7589447","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents a novel dual direction silicon-controlled rectifier device for electrostatic discharge (ESD) protection. An additional p-type ESD implantation layer was added to realize the proposed device (EDDSCR), playing the role of P-well in the traditional Dual SCR. A modified EDDSCR (MEDDSCR) with lower trigger voltage by inserted a PMOS is also proposed. TCAD simulation indicates that the proposed device has advantages of low trigger voltage, low conduction resistance, and good latch-up immunity, making it very suitable for ESD protection in I/O and Core circuits of 28 nm CMOS process.