高压集成电路的片上ESD保护设计

2016 IEEE International Nanoelectronics Conference (INEC) Pub Date : 2016-05-09 DOI:10.1109/INEC.2016.7589428

M. Ker

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引用次数: 1

摘要

静电放电(ESD)保护一直是CMOS集成电路的重要可靠性问题，特别是在高压(HV)应用中。在这个特邀演讲中，简要介绍了高压集成电路的ESD保护设计。在高压集成电路产品的实际应用中，强调了有用和安全的解决方案。

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On-chip ESD protection design for HV integrated circuits

Electrostatic discharge (ESD) protection has been an important reliability issue to CMOS integrated circuits, especially in high-voltage (HV) applications. In this invited talk, a brief overview on ESD protection designs for HV integrated circuits is presented. The useful and safe solutions are highlighted for real applications in HV IC products.

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2016 IEEE International Nanoelectronics Conference (INEC)

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