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2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)最新文献

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The design of logic gates using Single Electron Box (SEB) Nano-Devices 用单电子盒(SEB)纳米器件设计逻辑门
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941436
S. Rehan
{"title":"The design of logic gates using Single Electron Box (SEB) Nano-Devices","authors":"S. Rehan","doi":"10.1109/DTIS.2011.5941436","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941436","url":null,"abstract":"The Single Electron Box (SEB) is the basic functional Single Electron Nano-Devices (SENDs). In this paper, a detailed analysis of the SEB basic operation is reviewed. The SEB with extra input capacitors is presented with adjusted parameters so as to get same digital levels for both inputs and outputs. Both NOT and NAND logic gates followed by a double-inverter stage are proposed. The detailed schematic diagrams along with the corresponding simulation results (using SIMON 2.0) of these SEB logic gates are included.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115287044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Keynote speech 1: Leakage power in nanometric CMOS: Challenges and trends 主题演讲1:纳米CMOS的泄漏功率:挑战与趋势
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941402
J. Figueras
{"title":"Keynote speech 1: Leakage power in nanometric CMOS: Challenges and trends","authors":"J. Figueras","doi":"10.1109/DTIS.2011.5941402","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941402","url":null,"abstract":"As technology is scaled down in the nanometric dimensions of the devices, the variability of the manufacturing process on the circuit parameters becomes critical. In addition, environmental changes in power supply voltages and temperature on chip gradients add new uncertainties on future electronic circuits and systems. The VLSI design paradigms are to be profoundly revised. The classical “design margin” approach to compensate for uncertainty becomes ineffective and costly. An emerging design approach consists in the provision of “on-chip adaptivity” to compensate dynamically to variability: Process parameters, Voltage, Temperature and Aging (PVTA).","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122070078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low voltage and low power DLL-based frequency synthesizer for covering VHF frequency band 覆盖甚高频频段的低电压低功率dll频率合成器
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941409
M. Gholami, M. Sharifkhani, M. Hashemi
{"title":"Low voltage and low power DLL-based frequency synthesizer for covering VHF frequency band","authors":"M. Gholami, M. Sharifkhani, M. Hashemi","doi":"10.1109/DTIS.2011.5941409","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941409","url":null,"abstract":"New architecture for a DLL based frequency synthesizer for wireless transceivers presents in this paper. This architecture has the advantages of occupy low area, low power, low voltage and low phase noise. DLLs are first ordered systems, so good stability can obtain in this design. This structure also can be used for generating fractional multiple of reference frequencies. The proposed circuit can operate at a substantially low supply voltage. As an example, the synthesizer is adopted to create the channel frequencies of French DVB-H/T standard. The circuit level and system level designs are presented. Also power consumption trade-offs are reported. It was shown that for the mentioned standard a mere 27 delay stages for VCDL is sufficient. Simulation results confirm the analytical predictions. The proposed DLL-based frequency synthesizer is implemented in a 0.13um CMOS technology.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126144053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Using design of experiment to diagnose analog blocks geometrical defects: Application to current reference circuits 用实验设计诊断模拟块几何缺陷:在电流参考电路中的应用
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941448
H. Aziza, J. Portal, K. Castellani-Coulié
{"title":"Using design of experiment to diagnose analog blocks geometrical defects: Application to current reference circuits","authors":"H. Aziza, J. Portal, K. Castellani-Coulié","doi":"10.1109/DTIS.2011.5941448","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941448","url":null,"abstract":"The purpose of this paper is to present an automated diagnosis methodology that targets analog blocks. An application example is given for a Current Reference (CR) circuit. The presented methodology focuses on speeding up the diagnosis process of anomalous variations of a CR outputs (i.e. the output current IREF, the consumption current ISUNK, the temperature dependency factor βT and the supply voltage dependency factor βV). This diagnosis methodology is based on a CR mathematical model which links specific CR design parameters to CR outputs. This model is generated thanks to a “Design Of Experiment” (DOE) technique. The DOE technique takes as input electrical simulation results of a CR circuit for different component geometries. DOE generates polynomial equations of the current reference outputs. Using these equations, the root cause of an anomalous CR output is detected in terms of CR design parameters.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127712215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Review of fault injection mechanisms and consequences on countermeasures design 故障注入机制及其对对策设计的影响
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941421
J. Dutertre, J. Fournier, A. Mirbaha, D. Naccache, J. Rigaud, B. Robisson, A. Tria
{"title":"Review of fault injection mechanisms and consequences on countermeasures design","authors":"J. Dutertre, J. Fournier, A. Mirbaha, D. Naccache, J. Rigaud, B. Robisson, A. Tria","doi":"10.1109/DTIS.2011.5941421","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941421","url":null,"abstract":"The secret keys handled by cryptographic devices can be extracted using fault attacks associated with cryptanalysis techniques. These faults can be induced by different means such as laser exposure, voltage or clock glitches, electromagnetic perturbation, etc. This paper provides a detailed insight into the physics and mechanisms involved in several fault injection processes. The paper also highlights the difficulty to design countermeasures while even hardware duplication, usually considered as secure, has proved to show flaws against low cost fault injection means.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122204137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Optimizing memory BIST Address Generator implementations 优化内存BIST地址生成器实现
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941430
A. van de Goor, H. Kukner, S. Hamdioui
{"title":"Optimizing memory BIST Address Generator implementations","authors":"A. van de Goor, H. Kukner, S. Hamdioui","doi":"10.1109/DTIS.2011.5941430","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941430","url":null,"abstract":"Memory Built-In Self-Test (MBIST) has become a standard industrial practice. Its quality is mainly determined by its fault detection capability in relationship to the the area overhead. The MBIST Address Generator (AG) is largely responsible for the fault detection capability, and has a significant contribution to the area overhead. This paper analyzes the properties and implementation aspects of several AGs. In addition, it presents a novel, very systematic, highspeed, low-power and low-overhead implementation, based on an Up-counter and a set of multiplexors.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"62 48","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131639423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A test technique and a BIST circuit to detect catastrophic faults in RF Mixers 一种检测射频混频器灾难性故障的测试技术和BIST电路
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941433
I. Liaperdos, L. Dermentzoglou, A. Arapoyanni, Y. Tsiatouhas
{"title":"A test technique and a BIST circuit to detect catastrophic faults in RF Mixers","authors":"I. Liaperdos, L. Dermentzoglou, A. Arapoyanni, Y. Tsiatouhas","doi":"10.1109/DTIS.2011.5941433","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941433","url":null,"abstract":"A test technique and a Built-In Self-Test (BIST) circuit to detect catastrophic faults in RF Mixers is presented in this paper. During test application the Mixer is set to operate in homodyne mode and the DC levels generated at its outputs are used as test observables. These test observables are converted to digital signatures, by a simple embedded circuit, and are used to discriminate fault free from faulty Mixers. The proposed technique has been applied to a typical differential RF Mixer designed in a 0.18μm CMOS technology. Simulation results validated its efficiency to provide a high coverage of catastrophic faults which exceeds 90%.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121383894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
New transient detection circuit to detect ESD-induced disturbance for automatic recovery design in display panels 新型瞬态检测电路检测显示面板中静电干扰的自动恢复设计
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941441
Cheng-Cheng Yen, Wan-Yen Lin, M. Ker, Che-Ming Yang, Shih-Fan Chen, Tung-Yang Chen
{"title":"New transient detection circuit to detect ESD-induced disturbance for automatic recovery design in display panels","authors":"Cheng-Cheng Yen, Wan-Yen Lin, M. Ker, Che-Ming Yang, Shih-Fan Chen, Tung-Yang Chen","doi":"10.1109/DTIS.2011.5941441","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941441","url":null,"abstract":"A new transient detection circuit against system-level electrostatic discharge (ESD) transient disturbance is proposed for display panel protection. The circuit function to detect positive or negative electrical transients under system-level ESD tests has been evaluated in HSPICE simulation and verified in 0.13-nm silicon chip. The output signal of the proposed transient detection circuit can be used as a firmware index to execute system automatic recovery operation. With hardware/firmware system co-design, the immunity of display panels against transient disturbance under system-level ESD tests can be enhanced.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115982130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new method for noise analysis in nano-scale VLSI circuits using wavelet 一种基于小波的纳米级VLSI电路噪声分析新方法
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941440
A. Haghayegh, B. Forouzandeh, D. Fathi, Kaveh Kangarloo
{"title":"A new method for noise analysis in nano-scale VLSI circuits using wavelet","authors":"A. Haghayegh, B. Forouzandeh, D. Fathi, Kaveh Kangarloo","doi":"10.1109/DTIS.2011.5941440","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941440","url":null,"abstract":"This paper analyzes signals in nanometer VLSI circuits using wavelet techniques; afterwards, noise source (aggressor line) and interconnect effects are studied. As becoming integrated circuits denser, using nanometer scale technologies, shrinking dimensions of interconnects, the role of interconnect parasitic effects in the signal integrity at high speeds, become increasingly significant which may result in the aggravation of crosstalk noise amplitude and duration, and the circuit faults. Using wavelet transform techniques in signal analysis and several simulations of the interconnect output signals, the proposed wavelet-based approach precisely and also clearly defines which interconnects are considered as the victim lines and which ones as the aggressor lines, and each interconnect can also be numbered. The effect of both the series resistance and the output parasitic capacitance of the driver has been taken into account for an accurate modeling of the VLSI interconnect line.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116017846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Yield improvement and test cost reduction for TSV based 3D stacked ICs 基于TSV的3D堆叠集成电路的良率提高和测试成本降低
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941404
S. Hamdioui
{"title":"Yield improvement and test cost reduction for TSV based 3D stacked ICs","authors":"S. Hamdioui","doi":"10.1109/DTIS.2011.5941404","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941404","url":null,"abstract":"The industry is preparing itself for three-dimensional stacked ICs (3D-SICs), vertically interconnected by means of Through-Silicon Via's (TSVs). 3D-SIC is an emerging technology that promises heterogeneous integration with higher performance and lower power dissipation at a smaller footprint [1], [2]. Examples of 3D-SICs include 3D CMOS sensors [3], 3D FPGAs [3], 3D processors [4], 3D cache and memory [5], [6], and combined stacks of memories and processors [3], [7]. 3D-SICs can be manufactured using three different stacking approaches: Wafer-to-Wafer (W2W), Die-to-Wafer (D2W) or Die-to-Die (D2D) stacking. Each stacking approach has its benefits and drawbacks [3], [9], [8]. The major benefit of W2W is the high manufacturing throughput and the ability to handle small dies. However, it suffers from low compound yield. In D2D a high yield can be obtained due to Known Good Die (KGD) stacking, but the throughput is expected to be low. The manufacturing throughput in D2W settles between D2D and W2W, and results in similar yields as in D2D due to the same ability of KGD stacking.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131076442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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