Low voltage and low power DLL-based frequency synthesizer for covering VHF frequency band

M. Gholami, M. Sharifkhani, M. Hashemi
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引用次数: 12

Abstract

New architecture for a DLL based frequency synthesizer for wireless transceivers presents in this paper. This architecture has the advantages of occupy low area, low power, low voltage and low phase noise. DLLs are first ordered systems, so good stability can obtain in this design. This structure also can be used for generating fractional multiple of reference frequencies. The proposed circuit can operate at a substantially low supply voltage. As an example, the synthesizer is adopted to create the channel frequencies of French DVB-H/T standard. The circuit level and system level designs are presented. Also power consumption trade-offs are reported. It was shown that for the mentioned standard a mere 27 delay stages for VCDL is sufficient. Simulation results confirm the analytical predictions. The proposed DLL-based frequency synthesizer is implemented in a 0.13um CMOS technology.
覆盖甚高频频段的低电压低功率dll频率合成器
本文提出了一种基于DLL的无线收发器频率合成器的新结构。该结构具有占地面积小、功耗低、电压低、相位噪声低等优点。dll是一阶系统,因此在本设计中可以获得良好的稳定性。这种结构也可用于产生参考频率的分数倍。所提出的电路可以在相当低的电源电压下工作。以该合成器创建法国DVB-H/T标准的信道频率为例。给出了电路级和系统级的设计。此外,还报告了功耗权衡。结果表明,对于上述标准,仅27个延迟阶段的VCDL是足够的。仿真结果证实了分析预测。所提出的基于dll的频率合成器采用0.13um CMOS技术实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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