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2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)最新文献

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Calibration and post processing approaches for current and voltage mode A/D converters 电流和电压模式A/D转换器的校准和后处理方法
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941414
N. Petrellis, M. Birbas
{"title":"Calibration and post processing approaches for current and voltage mode A/D converters","authors":"N. Petrellis, M. Birbas","doi":"10.1109/DTIS.2011.5941414","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941414","url":null,"abstract":"A voltage and a current mode A/D Converter based on a novel integer divider circuit have been recently proposed by the authors. The mismatch and process or temperature variation problems have to be considered during the design as well as the real time operation since they affect the linearity of the conversion and in extreme cases they can lead to complete operation failure. A number of current and voltage mode calibration and post processing techniques that can be applied to several A/D Conversion architectures have been designed, based on the behavior of the proposed converters. The calibration methods can guarantee the correct real time operation of these converters while the presented post processing technique improves by up to 6dB the achieved Signal to Noise and Distortion Ratio of an 8-bit ADC designed by the authors.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127018151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel methodology for architecture-level exploration of 3D SoCs 一种架构级探索3D soc的新方法
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941425
Dionisis Diamantopoulos, K. Siozios, D. Bekiaris, D. Soudris
{"title":"A novel methodology for architecture-level exploration of 3D SoCs","authors":"Dionisis Diamantopoulos, K. Siozios, D. Bekiaris, D. Soudris","doi":"10.1109/DTIS.2011.5941425","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941425","url":null,"abstract":"Three-dimensional (3D) integration is an emerging technology that is expected to lead to tremendous benefits in terms of power, delay and silicon area. Moreover, 3D technology continues interconnect advances beyond the CMOS scaling predicted by Moore's Law, which enable new capabilities not available in 2D ICs. This paper proposes a physical design framework that enables rapid evaluation of 3D SOCs under different optimization goals. For demonstration purposes we apply the proposed framework for the 3D physical design of an embedded processor. Experimental results shown that 3D integration can alleviate the constraints posed by increased wire-length, such as power consumption, by about 20% compared to the 2D implementation.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"262 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122661162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Keynote speech 2: Reconfigurable systems and 3D architectures 主题演讲2:可重构系统和3D架构
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941403
D. Soudris
{"title":"Keynote speech 2: Reconfigurable systems and 3D architectures","authors":"D. Soudris","doi":"10.1109/DTIS.2011.5941403","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941403","url":null,"abstract":"Three-dimensional (3-D) integration has emerged as a revolutionary technology that can satisfy these requirements. The shift from horizontal scaling to volumetric stacking of circuits has the potential to mitigate the many limitations of modern integrated circuits. 3-D architectures contain multiple physical layers and offer considerable improvement in circuit performance, such as lower power/energy consumption, less total wire-length, higher integration density, and greater speed comparing with two-dimensional (2-D) circuits.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127755311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel parallel architecture for low voltage-low power DLL-based frequency multiplier 一种新型的低压低功率dll倍频器并行结构
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941408
M. Gholami, M. Sharifkhani, M. Hashemi
{"title":"A novel parallel architecture for low voltage-low power DLL-based frequency multiplier","authors":"M. Gholami, M. Sharifkhani, M. Hashemi","doi":"10.1109/DTIS.2011.5941408","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941408","url":null,"abstract":"New architecture for a DLL based frequency multiplier for wireless transceivers presents in this paper. This architecture has the advantages of occupy low area, low power, low voltage and low phase noise. DLLs are first ordered systems, so good stability can obtain in this design. This structure also can be used for generating big multiple of reference frequencies. The proposed circuit can operate at a substantially low supply voltage. As an example, the multiplier is adopted to create the 13 times of the reference frequency. The circuit level design is presented. Also power consumption trade-offs are reported. Simulation results confirm the analytical predictions. The proposed DLL-based frequency multiplier is implemented in a 0.13um CMOS Technology.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125459472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
RFID implantable pressure sensor for the follow-up of abdominal aortic aneurysm stented 射频识别植入式压力传感器用于腹主动脉瘤支架置入的随访
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941418
O. Romain, J. Mazeyrat, P. Garda, H. Talleb, D. Lautru, M. Wong, J. Wiart, V. Hanna, P. Lagrée, M. Bonneau, C. Kang, Miguel Fernandez, Jean-Frédéric Gerbeau, V. Deplano, B. Berthier, C. Legallais, P. Leprince
{"title":"RFID implantable pressure sensor for the follow-up of abdominal aortic aneurysm stented","authors":"O. Romain, J. Mazeyrat, P. Garda, H. Talleb, D. Lautru, M. Wong, J. Wiart, V. Hanna, P. Lagrée, M. Bonneau, C. Kang, Miguel Fernandez, Jean-Frédéric Gerbeau, V. Deplano, B. Berthier, C. Legallais, P. Leprince","doi":"10.1109/DTIS.2011.5941418","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941418","url":null,"abstract":"An abdominal aortic aneurysm (AAA) is a dilatation of the aorta at the abdominal level, the rupture of which is a life threatening complication with an 80% mortality rate. Even though those devices keep improving, the failure rate of the endovascular treatment is due to persisting pressure into the excluded aneurysmal sac. Since 2005, several integrated sensors have been designed for the follow-up of the AAA treated by a stent. Solutions are based on the use of a single sensor. Thrombus in the excluded AAA can modify the field of pressure when leaks appeared and a network of sensors should be used. We present in this paper the ENDOCOM project that aims to design an implantable pressure sensor that can be used in a network configuration. To validate the new materials, we developed a framework composed of in vitro experiments and in vivo tests on large animal model. Numerical modeling has been investigated from the experimental data to determine the optimal position of sensor. Some results of those different parts are shown in this paper.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134233357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Formal generation of synthesizable RTL from regular programs 从常规程序正式生成可合成RTL
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941415
Michael F. Dossis
{"title":"Formal generation of synthesizable RTL from regular programs","authors":"Michael F. Dossis","doi":"10.1109/DTIS.2011.5941415","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941415","url":null,"abstract":"The complexity of the contemporary digital circuits and systems, determines the need for higher specification abstraction and automatic circuit synthesis techniques to be adopted. A prototype high level synthesis framework is presented here, that automatically generates synthesizable RTL code from unaltered, high level programs. The framework is developed using compiler-generator and logic programming (thus formal) techniques, and it utilizes a patented intermediate compilation format to retain the algorithmic semantics of the source programs and allow for compiler transformations. The synthesis framework is evaluated via statistics from a number of real-life applications. The performance optimization of the compiled applications, including an MPEG engine, underlines the quality of the prototype design framework.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131556359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A test solution for oxide thickness variations in the ATMEL TSTAC™ eFlash technology ATMEL TSTAC™eFlash技术中氧化物厚度变化的测试解决方案
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941431
Pierre-Didier Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, B. Godard, G. Festes, L. Vachez
{"title":"A test solution for oxide thickness variations in the ATMEL TSTAC™ eFlash technology","authors":"Pierre-Didier Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, B. Godard, G. Festes, L. Vachez","doi":"10.1109/DTIS.2011.5941431","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941431","url":null,"abstract":"The embedded Flash (eFlash) technologies are based on the Floating Gate (FG) concept and can be subject to defects leading to retention and reliability problems. One of the most important aspects to guarantee high retention and reliability levels is the oxide thickness where the electric field is applied for charge injection and removal. In this paper, we analyze the impact of a defective oxide thickness on memory core cells built with the ATMEL TSTAC™ technology. We show how this variation of oxide thickness impacts the erase and write operations and consequently, the retention and the reliability of the memory. Then, we propose a test solution able to characterize and test the oxide thickness. This solution consists in adapting the inhibition voltage of non-selected bit lines during write operations.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114450182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Exploring the effect of LUT and arity size on a tree-based application specific inflexible FPGA 探索LUT和密度大小对基于树的特定应用的非灵活FPGA的影响
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941426
Umer Farooq, H. Parvez, Emna Amouri, H. Mehrez, Z. Marrakchi
{"title":"Exploring the effect of LUT and arity size on a tree-based application specific inflexible FPGA","authors":"Umer Farooq, H. Parvez, Emna Amouri, H. Mehrez, Z. Marrakchi","doi":"10.1109/DTIS.2011.5941426","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941426","url":null,"abstract":"An application specific inflexible FPGA (ASIF) is an FPGA with reduced flexibility and improved density. An ASIF is reduced from an FPGA for a predefined set of applications that operate at mutually exclusive times. This work presents a new tree-based ASIF and uses a set of 16 MCNC benchmarks to explore the effect of lookup table (LUT) and arity size on it and results are then compared with those of mesh-based ASIF. For tree-based ASIF, LUT size is varied from 3 to 7 while arity size is varied from 4 to 8 and 16. Experimental results show that smaller LUTs with higher arity sizes produce good area results but poor performance results. Finally experimental results show that LUT 4 with arity 16 gives best area-delay product and compared to mesh-based ASIF, this combination gives 12% routing area gain.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129374914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and implementation of an OFDM system for vehicular communications with FPGA technologies 基于FPGA技术的车载通信OFDM系统的设计与实现
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941446
G. Kiokes, G. Economakos, A. Amditis, N. Uzunoglu
{"title":"Design and implementation of an OFDM system for vehicular communications with FPGA technologies","authors":"G. Kiokes, G. Economakos, A. Amditis, N. Uzunoglu","doi":"10.1109/DTIS.2011.5941446","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941446","url":null,"abstract":"This paper presents design and implementation results of an Orthogonal Frequency Division Multiplexing (OFDM) system customized for vehicular ad-hoc networks, based on the IEEE 802.11p standard specifications. The 802.11p is based on the widely spread IEEE 802.11a and intends to support both public safety and licensed private operations over communication channels. OFDM achieves very efficient use of the allocated bandwidth and the main advantage is its robustness to frequency selectivity in wireless environment, like in the case of vehicular communications. The OFDM transceiver implementation presented in this paper is based on FPGA technology and the VHDL hardware description language. The hardware modules designed include QPSK modulator-demodulator, serial to parallel converter, FFT, IFFT. The use of reconfigurable FPGA devices and VHDL descriptions allowed a large number of tests to be carried out for each module, in order to obtain optimum results. The final implementation consists of two identical Xilinx Virtex-4 FPGA development boards (one for the receiver and one for the transmitter), offering among others dual channel high performance ADCs and DACs, required for operation in the licensed ITS band of 5.9 GHz.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122200477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A wideband and SPICE-compatible model for interconnect coupling prediction in nanoscale VLSI circuits up to 60 GHz 用于60ghz纳米级VLSI电路互连耦合预测的宽带和spice兼容模型
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/ICOM.2011.5995293
Yiorgos I. Bontzios, M. Dimopoulos, A. Dimitriadis, A. Hatzopoulos
{"title":"A wideband and SPICE-compatible model for interconnect coupling prediction in nanoscale VLSI circuits up to 60 GHz","authors":"Yiorgos I. Bontzios, M. Dimopoulos, A. Dimitriadis, A. Hatzopoulos","doi":"10.1109/ICOM.2011.5995293","DOIUrl":"https://doi.org/10.1109/ICOM.2011.5995293","url":null,"abstract":"A new lumped model fully compatible with SPICE-like simulators is proposed in this work. The model is scalable, technology independent and can unify predict both capacitive and inductive coupling effects. It is validated up to 60 GHz by means of two commercial EM simulators.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"298 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132690999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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