ATMEL TSTAC™eFlash技术中氧化物厚度变化的测试解决方案

Pierre-Didier Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, B. Godard, G. Festes, L. Vachez
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引用次数: 1

摘要

嵌入式Flash (eFlash)技术基于浮动门(FG)概念,可能存在导致保留和可靠性问题的缺陷。保证高保留和可靠性水平的最重要方面之一是电场用于电荷注入和去除的氧化层厚度。在本文中,我们分析了缺陷氧化物厚度对使用ATMEL TSTAC™技术构建的存储核心电池的影响。我们展示了这种氧化物厚度的变化如何影响擦除和写入操作,从而影响存储器的保留和可靠性。然后,我们提出了一种能够表征和测试氧化物厚度的测试方案。该解决方案包括在写操作期间调整非选择位线的抑制电压。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A test solution for oxide thickness variations in the ATMEL TSTAC™ eFlash technology
The embedded Flash (eFlash) technologies are based on the Floating Gate (FG) concept and can be subject to defects leading to retention and reliability problems. One of the most important aspects to guarantee high retention and reliability levels is the oxide thickness where the electric field is applied for charge injection and removal. In this paper, we analyze the impact of a defective oxide thickness on memory core cells built with the ATMEL TSTAC™ technology. We show how this variation of oxide thickness impacts the erase and write operations and consequently, the retention and the reliability of the memory. Then, we propose a test solution able to characterize and test the oxide thickness. This solution consists in adapting the inhibition voltage of non-selected bit lines during write operations.
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