A novel methodology for architecture-level exploration of 3D SoCs

Three-dimensional (3D) integration is an emerging technology that is expected to lead to tremendous benefits in terms of power, delay and silicon area. Moreover, 3D technology continues interconnect advances beyond the CMOS scaling predicted by Moore's Law, which enable new capabilities not available in 2D ICs. This paper proposes a physical design framework that enables rapid evaluation of 3D SOCs under different optimization goals. For demonstration purposes we apply the proposed framework for the 3D physical design of an embedded processor. Experimental results shown that 3D integration can alleviate the constraints posed by increased wire-length, such as power consumption, by about 20% compared to the 2D implementation.