{"title":"用单电子盒(SEB)纳米器件设计逻辑门","authors":"S. Rehan","doi":"10.1109/DTIS.2011.5941436","DOIUrl":null,"url":null,"abstract":"The Single Electron Box (SEB) is the basic functional Single Electron Nano-Devices (SENDs). In this paper, a detailed analysis of the SEB basic operation is reviewed. The SEB with extra input capacitors is presented with adjusted parameters so as to get same digital levels for both inputs and outputs. Both NOT and NAND logic gates followed by a double-inverter stage are proposed. The detailed schematic diagrams along with the corresponding simulation results (using SIMON 2.0) of these SEB logic gates are included.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"The design of logic gates using Single Electron Box (SEB) Nano-Devices\",\"authors\":\"S. Rehan\",\"doi\":\"10.1109/DTIS.2011.5941436\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Single Electron Box (SEB) is the basic functional Single Electron Nano-Devices (SENDs). In this paper, a detailed analysis of the SEB basic operation is reviewed. The SEB with extra input capacitors is presented with adjusted parameters so as to get same digital levels for both inputs and outputs. Both NOT and NAND logic gates followed by a double-inverter stage are proposed. The detailed schematic diagrams along with the corresponding simulation results (using SIMON 2.0) of these SEB logic gates are included.\",\"PeriodicalId\":409387,\"journal\":{\"name\":\"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)\",\"volume\":\"84 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DTIS.2011.5941436\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTIS.2011.5941436","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The design of logic gates using Single Electron Box (SEB) Nano-Devices
The Single Electron Box (SEB) is the basic functional Single Electron Nano-Devices (SENDs). In this paper, a detailed analysis of the SEB basic operation is reviewed. The SEB with extra input capacitors is presented with adjusted parameters so as to get same digital levels for both inputs and outputs. Both NOT and NAND logic gates followed by a double-inverter stage are proposed. The detailed schematic diagrams along with the corresponding simulation results (using SIMON 2.0) of these SEB logic gates are included.