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Implementation of a threaded dataflow multiprocessor using FPGAs 用fpga实现多线程数据流多处理器
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941444
K. Tatas, C. Kyriacou
{"title":"Implementation of a threaded dataflow multiprocessor using FPGAs","authors":"K. Tatas, C. Kyriacou","doi":"10.1109/DTIS.2011.5941444","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941444","url":null,"abstract":"This paper presents the FPGA implementation and evaluation of the prototype for a Data-Driven Multithreading Chip-Multiprocessor. In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that enables thread execution using dataflow rules on a chip multiprocessor. Threads are scheduled for execution based on data availability, i.e. a thread is fired only if its input data is available. This model of execution is called the non-blocking Data-Driven Multithreading (DDM) model of execution. Due to its dataflow characteristics, this model exploits parallelism and tolerates latency. The DDM model has been evaluated using an execution driven simulator and showed and average speedup of 26 on a 32-node system. For evaluation purposes, implementation on Xilinx Virtex-5 FPGA using the Microblaze processors as execution cores has been performed. Experimental results show that the TSU can be implemented with a moderate hardware budget, and that delays incurred by the operation of the TSU can be tolerated. Furthermore, hardware complexity evaluation shows that the TSU size scales very well with the number of processors in the MPSoC.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130294719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Vade mecum on side-channels attacks and countermeasures for the designer and the evaluator 为设计人员和评估人员提供关于侧信道攻击和对策的建议
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941419
S. Guilley, O. Meynard, Maxime Nassar, Guillaume Duc, P. Hoogvorst, Houssem Maghrebi, Aziz Elaabid, S. Bhasin, Youssef Souissi, Nicolas Debande, L. Sauvage, J. Danger
{"title":"Vade mecum on side-channels attacks and countermeasures for the designer and the evaluator","authors":"S. Guilley, O. Meynard, Maxime Nassar, Guillaume Duc, P. Hoogvorst, Houssem Maghrebi, Aziz Elaabid, S. Bhasin, Youssef Souissi, Nicolas Debande, L. Sauvage, J. Danger","doi":"10.1109/DTIS.2011.5941419","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941419","url":null,"abstract":"Implementation-level attacks are nowadays well known and most designers of security embedded systems are aware of them. However, both the number of vulnerabilities and of protections have seriously grown since the first public reporting of these threats in 1996. It is thus difficult to assess the correct countermeasures association to cover all the possible attack paths. The goal of this paper is to give a clear picture of the possible adequation between actually risks and mitigation techniques. A specific focus is made on two protection techniques addressing primarily side-channel attacks: masking and hiding. For the first time, we provide with a way to estimate a tradeoff depending on the environmental conditions (amount of noise) and on the designer skills (ability to balance the design). This tradeoff is illustrated in a decision diagram, helpful for the security designer to justify choices and to account for the cost overhead.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"21 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116581161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Embedded tutorial 3: Statistical learning for analog circuit testing 嵌入式教程3:模拟电路测试的统计学习
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941406
H. Stratigopoulos
{"title":"Embedded tutorial 3: Statistical learning for analog circuit testing","authors":"H. Stratigopoulos","doi":"10.1109/DTIS.2011.5941406","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941406","url":null,"abstract":"The test cost per transistor in integrated circuits (IC) has remained practically steady during the past decades, unlike the manufacturing cost per transistor which is gradually being reduced. In recent years, there have been anecdotal cases where the test cost actually surpasses the overall manufacturing cost. To this end, test cost reduction is a significant driving force for the deployment of ICs in a wider range of applications for the broad public. It is also a fact that the cost for testing the analog portions of an IC can amount up to 50% of the total test cost, despite that analog circuits occupy typically less than 5% of the die area. This shows that analog test is in the coming years an area for industry focus, innovation and improvement.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129605337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Carbon-based Schottky barrier transistor: From compact modeling to digital circuit applications 碳基肖特基势垒晶体管:从紧凑建模到数字电路应用
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941435
S. Frégonèse, C. Maneux, T. Zimmer, M. Najari, H. Mnif, N. Masmoudi
{"title":"Carbon-based Schottky barrier transistor: From compact modeling to digital circuit applications","authors":"S. Frégonèse, C. Maneux, T. Zimmer, M. Najari, H. Mnif, N. Masmoudi","doi":"10.1109/DTIS.2011.5941435","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941435","url":null,"abstract":"This paper presents a comprehensive approach starting from compact model development for the Schottky barrier carbon nanotube field effect transistor (SB-CNTFET) to digital circuit simulation. The present compact model is essentially based on a novel formulation of the channel density of charge (Qcnt). This Qcnt is solved analytically using approximations for the transmission function T(E). Then, the compact model is used to simulate basic logical inverter gate. Thus, the influence of the Schottky barrier features (SB) on the voltage transfer characteristic (VTC) has been highlighted. Six transistor static memory cell (6T-SRAM) is presented and simulated on either read and write operations. Finally, for the assessment of the SB on the 6T-SRAM performances, transient power consumption results are compared with those of the conventional CNTFET with zero-SB height.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126642488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Adaptive numerical integration methods for deterministic analysis of non-stationary noise in dynamic integrated circuits 动态集成电路非平稳噪声确定性分析的自适应数值积分方法
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941412
A. Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs
{"title":"Adaptive numerical integration methods for deterministic analysis of non-stationary noise in dynamic integrated circuits","authors":"A. Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs","doi":"10.1109/DTIS.2011.5941412","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941412","url":null,"abstract":"This paper reports a new step-size control strategy for adaptive numerical integration in time-domain noise analysis of non-linear dynamic integrated circuits with arbitrary excitations. A non-stationary stochastic noise process is described as an Itô system of stochastic differential equations and a numerical solution for such a set of equations is found. Statistical simulation of dynamic circuits fabricated in 45 nm CMOS process shows that the proposed numerical methods offer an accurate and efficient solution.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129110178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A mixed signal multiplier using A2 binary representation dedicated to neural networks applications 一个使用A2二进制表示的混合信号乘法器，专用于神经网络应用
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941407
Hatem Boukadida, N. Hassen, Z. Gafsi, K. Besbes
{"title":"A mixed signal multiplier using A2 binary representation dedicated to neural networks applications","authors":"Hatem Boukadida, N. Hassen, Z. Gafsi, K. Besbes","doi":"10.1109/DTIS.2011.5941407","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941407","url":null,"abstract":"The main goal of our work is to investigate the delay performances of redundant binary arithmetic operators using different CMOS logic and mixed signals styles. This paper presents a novel technique for A2 redundant binary multiplication in mixed-signal circuits especially for neural networks applications. The proposed multiplier consists of three cascaded blocks: Two 3-bit Arithmetic Multiplier Digital to Analog Converter (AMDAC) cells, and one 6-bit Flash ADC. Our technique indicates that this approach significantly reduces the silicon area occupied by such multipliers compared to the classical scheme using combinational multipliers. The circuit being studied is optimized for speed efficiency at 0.35μm CMOS process.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"79 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115828048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Poly-Silicon gate pre-doping implantation impact on MOSFET matching performances 多晶硅栅极预掺杂注入对MOSFET匹配性能的影响
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941437
Y. Joly, J. Delalleau, L. Lopez, J. Portal, H. Aziza, Y. Bert, F. Julien, P. Fornara
{"title":"Poly-Silicon gate pre-doping implantation impact on MOSFET matching performances","authors":"Y. Joly, J. Delalleau, L. Lopez, J. Portal, H. Aziza, Y. Bert, F. Julien, P. Fornara","doi":"10.1109/DTIS.2011.5941437","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941437","url":null,"abstract":"This paper demonstrates how poly-Silicon gate pre-doping implantation impacts MOS matching performances. Measurements are performed on test structures (MOS pairs / capacitors) and analog circuits, using five different processes with pre-doping implantation energy variation (from 35 to 10 KeV) and tilt variation (7° and 25°). TCAD simulations validate a channel counter-doping due to high pre-doping implantation energy causing mismatch degradation.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126164272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study 通过可配置晶体管阵列规则结构的快速上市时间:一个延迟锁定环路设计案例研究
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941428
M. Pons, E. Barajas, D. Mateo, J. L. Gonzalez, F. Moll, A. Rubio, J. Abella, X. Vera, A. González
{"title":"Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study","authors":"M. Pons, E. Barajas, D. Mateo, J. L. Gonzalez, F. Moll, A. Rubio, J. Abella, X. Vera, A. González","doi":"10.1109/DTIS.2011.5941428","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941428","url":null,"abstract":"Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison with a full custom design demonstrates that VCTA can be used without loss of functionality while accelerating the design time. Layout implementations, in 90nm CMOS process, as well as the delay, energy and jitter electrical simulations are provided.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127069494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 3D Network-on-Chip for stacked-die transactional chip multiprocessors using Through Silicon Vias 一种采用硅通孔的用于堆叠式事务性芯片多处理器的三维片上网络
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941443
Sumeet S. Kumar, R. van Leuken
{"title":"A 3D Network-on-Chip for stacked-die transactional chip multiprocessors using Through Silicon Vias","authors":"Sumeet S. Kumar, R. van Leuken","doi":"10.1109/DTIS.2011.5941443","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941443","url":null,"abstract":"Effective utilization of computing power offered by modern chip multiprocessors (CMP) depends on the design and performance of the interconnect that connects them. We present a three-dimensional Network-on-Chip (NoC) based on the R3 router architecture for transactional CMPs utilizing advanced Through Silicon Vias (TSV) in a stacked-die architecture, facilitating low latency and high throughput communication between CMP nodes. We report the performance of an R3 based three-dimensional mesh in a stacked-die transactional CMP highlighting the limitations of performance scale-up with stacking. Furthermore, we present data on area penalty associated with the use of TSVs in different configurations in 90nm UMC technology.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130795796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
GPRS performance optimization with pre-empted packet queue analysis GPRS性能优化与抢先包队列分析
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941423
K. Aggelis, S. Louvros
{"title":"GPRS performance optimization with pre-empted packet queue analysis","authors":"K. Aggelis, S. Louvros","doi":"10.1109/DTIS.2011.5941423","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941423","url":null,"abstract":"Queue performance for radio resource allocation is analysed in GPRS network. In this case GSM traffic (voice priority) priority is considered higher than GPRS packet traffic and already served packets could be pre-empted and enter a queue. Using two dimensional Markov chain with packet queue of length Q pre-empted packets could be saved and re-enter into service in later time periods. Optimizing Queue length will lead into less power consumption of UE handsets","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128497735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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