Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

Abstract

Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison with a full custom design demonstrates that VCTA can be used without loss of functionality while accelerating the design time. Layout implementations, in 90nm CMOS process, as well as the delay, energy and jitter electrical simulations are provided.