通过可配置晶体管阵列规则结构的快速上市时间:一个延迟锁定环路设计案例研究

2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI:10.1109/DTIS.2011.5941428

M. Pons, E. Barajas, D. Mateo, J. L. Gonzalez, F. Moll, A. Rubio, J. Abella, X. Vera, A. González

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引用次数: 5

摘要

上市时间是当今集成电路制造商面临的一个关键问题。本文研究了一种可配置晶体管阵列规则布局结构(VCTA)的延迟锁相环设计(DLL)，以最大限度地缩短产品上市时间和相关成本。与完全定制设计的比较表明，VCTA可以在不损失功能的情况下使用，同时加快设计时间。给出了在90nm CMOS工艺下的布局实现，以及延迟、能量和抖动的电学模拟。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison with a full custom design demonstrates that VCTA can be used without loss of functionality while accelerating the design time. Layout implementations, in 90nm CMOS process, as well as the delay, energy and jitter electrical simulations are provided.

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2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)

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