2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)最新文献_第4页

How significant will be the test cost share for 3D die-to-wafer stacked-ICs? 3D芯片到晶圆堆叠集成电路的测试成本份额有多大?

2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941432

M. Taouil, S. Hamdioui, E. Marinissen

{"title":"How significant will be the test cost share for 3D die-to-wafer stacked-ICs?","authors":"M. Taouil, S. Hamdioui, E. Marinissen","doi":"10.1109/DTIS.2011.5941432","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941432","url":null,"abstract":"Several challenges must be overcome before high volume production of the 3D Stacked-ICs (3D-SIC) can be realized. A key challenge is to guarantee the required product quality at minimal overall cost. Testing, which is an integral part of 3D-IC manufacturing, should be performed in such way that its cost contribution is optimal. This paper investigates the impact of different test moments for pre-bond and post-bond stacks (resulting into different test flows) on the overall cost of die-to-wafer (D2W) 3D-SICs. The investigation is carried out for a wide range of die yields and stack sizes. Moreover, a breakdown of the cost into manufacturing, test and packaging costs offers a more detailed picture of the 3D overall cost. Our simulation results show that overall cost in D2W stacking strongly depends on the selected test flow; test flows with pre-bond and post-bond tests show a higher test cost share, but a significant reduction in the overall 3D-SIC cost. In addition, the cost breakdown for our reference process reveals that the manufacturing cost is most dominant (between 76% and 85%), followed by test (between 13% and 19%). Moreover, the results show that the share of test and packaging decreases as the manufacturing becomes mature and the yield increases, and that both manufacturing and test cost share increases, while the packaging cost share decreases for higher stack sizes.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128616977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Automated model conversion for analogue simulation based on SPICE-level description 基于spice级描述的模拟仿真自动模型转换

2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941442

L. Xia, I. Bell, A. Wilkinson

引用次数: 1

Low-overhead two-dimensional test pattern generation 低开销的二维测试模式生成

2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941424

I. Voyiatzis, C. Efstathiou, G. Saousopoulos, H. Antonopoulou, K. Galanou

引用次数: 0

Cryptographic algorithms-on-a-chip: Architectures, designs & implementation platforms 芯片上的加密算法:架构、设计和实现平台

2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941405

N. Sklavos

引用次数: 7

Interconnect design for a 32 nm node technology 32纳米节点技术的互连设计

2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941410

D. Deschacht

引用次数: 0

CVD assisted fabrication of graphene layers for field effect device fabrication CVD辅助制备用于场效应器件的石墨烯层

2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941438

Pia Juliane Ginsel, Frank Wessely, Emrah Birinci, U. Schwalke

引用次数: 7

Advances in implanted functional electrical stimulation 植入式功能性电刺激的研究进展

2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941417

F. Soulier, S. Bernard, G. Cathébras, D. Guiraud

{"title":"Advances in implanted functional electrical stimulation","authors":"F. Soulier, S. Bernard, G. Cathébras, D. Guiraud","doi":"10.1109/DTIS.2011.5941417","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941417","url":null,"abstract":"Implanted functional electrical stimulation (FES) has been successfully used in a large set of applications linked to organic deficiencies and sensory disabilities. More recent attempts have been made to use implanted FES for movements or functions restoration in para- and quadriplegic patients. Unfortunately, standing and walking still remain unsatisfactory at the moment. Although not optimal, FES systems remain the only products on offer for movement restoration in a daily use context. The main drawbacks of the technique are well known and include insufficient reliability, the complexity of the surgery, limited stimulation selectivity and efficiency, non-physiological recruitment of motor units and the complexity of muscle control. To improve this selectivity, both electrode geometry and current shape have to be explored. A programmable multidimensional stimulus waveform generator provides the opportunity to conduct research on artificial-to-natural interfaces in order to achieve efficient and minimally aggressive activation. Thus, our team has developed a new architecture for advanced implanted FES: we designed and prototyped the basic elements of a network of distributed stimulation and measurement units. We designed the architecture taking into account the a priori constraints and requirements in terms of performance, safety, stimulation sites, as well as diversity in the stimulation profiles to address selectivity issues in nerve fiber recruitment. We choose a power-efficient microstimulator design where the stimulation current generated by a single source is then distributed on the outputs according to programmable ratios. The prototype circuit based on current mirrors guarantees constant ratios between channels all over the dynamic range. It uses a high-voltage technology (0.35 μm AMS HV) and can deal with adaptive power supply up to 20 V.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129462869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A reconfigurable IP characterization technique improving high-level synthesis results 一种可重构IP表征技术，可提高高水平合成结果

2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941416

Efstathios Sotiriou-Xanthopoulos, Ioannis Koutras, G. Economakos, D. Soudris

{"title":"A reconfigurable IP characterization technique improving high-level synthesis results","authors":"Efstathios Sotiriou-Xanthopoulos, Ioannis Koutras, G. Economakos, D. Soudris","doi":"10.1109/DTIS.2011.5941416","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941416","url":null,"abstract":"Reconfigurable computing is a cost-effective alternative to technology shrinking in order to achieve higher performance in digital design, especially considering run time reconfiguration. Research in the field consists of new reconfig-urable architectures, either coarse-grain or fine-grain, and new methodologies to map applications onto them. Usually, top-down methodologies are proposed, that start from the application's dataflow graph and try to merge different parts into the same reconfigurable component. This paper presents a bottom-up approach, that searches available RTL component libraries for primitives that can be connected in alternative ways and generate new components, with different modes of functionality. Such components, called morphable components, are designed to impose the minimum accepted area and timing overhead, without any reconfiguration overhead. The great advantage of the bottom-up approach is that it can be integrated easily with existing design methodologies and tools, offering great overall performance improvements. The results obtained with different DSP benchmarks in a high-level synthesis environment show an average performance gain of 15%, without any practical datapath area increase, offering uniform and balanced resource utilization.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130742831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Power-aware selection policy for networks on chip 芯片上网络的功率感知选择策略

2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941422

D. Salemi, M. Palesi, V. Catania

引用次数: 7

Implementation and efficiency evaluation of construction-based countermeasures against electromagnetic analysis 基于施工的电磁分析对策实施及效果评价

2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI: 10.1109/DTIS.2011.5941420

Amine Dehbaoui, S. Ordas, L. Torres, M. Robert, P. Maurine

{"title":"Implementation and efficiency evaluation of construction-based countermeasures against electromagnetic analysis","authors":"Amine Dehbaoui, S. Ordas, L. Torres, M. Robert, P. Maurine","doi":"10.1109/DTIS.2011.5941420","DOIUrl":"https://doi.org/10.1109/DTIS.2011.5941420","url":null,"abstract":"Side Channel Analysis (SCA) is a powerful class of attacks to extract cryptographic keys used in a wide variety of electronic devices that involves authentication, digital signatures or secure storage. Cryptographic systems are made up of cryptographic primitives implemented in Complementary Metal-Oxide-Semiconductor technology. But CMOS logic gates are designed to minimize their energy usage when their output does not change. Energy is consumed or dissipated mainly for the transitions ‘0 to 1’ and ‘1 to 0’. Side channel information like power consumption, electromagnetic radiation or light emission, changes the conventional black box model of a cryptographic system into a gray one. By this way, its possible to extract a secret key in a couple of hours. Within this context, this paper introduces the basic concepts of some interesting CMOS logic families, from a security point-of-view, and a design of a cryptographic system based on Secure Triple Track Logic (STTL). This logic is efficient against Differential Power Analysis (DPA), and evaluated in this work against Differential Electro Magnetic Analysis (DEMA) based on Difference of Means (DoM) and Correlation Electro Magnetic Analysis (CEMA).","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127465061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4