I. Voyiatzis, C. Efstathiou, G. Saousopoulos, H. Antonopoulou, K. Galanou
{"title":"Low-overhead two-dimensional test pattern generation","authors":"I. Voyiatzis, C. Efstathiou, G. Saousopoulos, H. Antonopoulou, K. Galanou","doi":"10.1109/DTIS.2011.5941424","DOIUrl":null,"url":null,"abstract":"Two-dimensional generators proposed to date have been based mainly on linear finite-state machines such as Linear Feedback Shift Registers, cellular automata, and ring generators. These mechanisms are usually accompanied by phase shifters in order to avoid the degradation of the fault coverage caused by correlations/dependences in the produced test bit sequences. Phase shifters insert unavoidable delay and hardware overhead in the resulting structure. In this paper we propose the utilization of accumulators whose inputs are driven by Linear Feedback Shift Registers as a candidate solution to the generation of 2D test patterns. The proposed scheme results in high period of the output sequence, and extremely low hardware overhead.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTIS.2011.5941424","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Two-dimensional generators proposed to date have been based mainly on linear finite-state machines such as Linear Feedback Shift Registers, cellular automata, and ring generators. These mechanisms are usually accompanied by phase shifters in order to avoid the degradation of the fault coverage caused by correlations/dependences in the produced test bit sequences. Phase shifters insert unavoidable delay and hardware overhead in the resulting structure. In this paper we propose the utilization of accumulators whose inputs are driven by Linear Feedback Shift Registers as a candidate solution to the generation of 2D test patterns. The proposed scheme results in high period of the output sequence, and extremely low hardware overhead.