优化内存BIST地址生成器实现

2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2011-04-06 DOI:10.1109/DTIS.2011.5941430

A. van de Goor, H. Kukner, S. Hamdioui

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引用次数: 20

摘要

内存内置自检(MBIST)已经成为标准的工业实践。它的质量主要取决于它的故障检测能力与架空面积的关系。MBIST地址发生器(AG)主要负责故障检测能力，对区域开销有很大贡献。本文分析了几种AGs的特性和实现方面。此外，本文还提出了一种新颖、系统、高速、低功耗、低开销的基于上行计数器和一组多路复用器的实现方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Optimizing memory BIST Address Generator implementations

Memory Built-In Self-Test (MBIST) has become a standard industrial practice. Its quality is mainly determined by its fault detection capability in relationship to the the area overhead. The MBIST Address Generator (AG) is largely responsible for the fault detection capability, and has a significant contribution to the area overhead. This paper analyzes the properties and implementation aspects of several AGs. In addition, it presents a novel, very systematic, highspeed, low-power and low-overhead implementation, based on an Up-counter and a set of multiplexors.

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来源期刊

2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)

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