A new method for noise analysis in nano-scale VLSI circuits using wavelet

Abstract

This paper analyzes signals in nanometer VLSI circuits using wavelet techniques; afterwards, noise source (aggressor line) and interconnect effects are studied. As becoming integrated circuits denser, using nanometer scale technologies, shrinking dimensions of interconnects, the role of interconnect parasitic effects in the signal integrity at high speeds, become increasingly significant which may result in the aggravation of crosstalk noise amplitude and duration, and the circuit faults. Using wavelet transform techniques in signal analysis and several simulations of the interconnect output signals, the proposed wavelet-based approach precisely and also clearly defines which interconnects are considered as the victim lines and which ones as the aggressor lines, and each interconnect can also be numbered. The effect of both the series resistance and the output parasitic capacitance of the driver has been taken into account for an accurate modeling of the VLSI interconnect line.