Yield improvement and test cost reduction for TSV based 3D stacked ICs

Abstract

The industry is preparing itself for three-dimensional stacked ICs (3D-SICs), vertically interconnected by means of Through-Silicon Via's (TSVs). 3D-SIC is an emerging technology that promises heterogeneous integration with higher performance and lower power dissipation at a smaller footprint [1], [2]. Examples of 3D-SICs include 3D CMOS sensors [3], 3D FPGAs [3], 3D processors [4], 3D cache and memory [5], [6], and combined stacks of memories and processors [3], [7]. 3D-SICs can be manufactured using three different stacking approaches: Wafer-to-Wafer (W2W), Die-to-Wafer (D2W) or Die-to-Die (D2D) stacking. Each stacking approach has its benefits and drawbacks [3], [9], [8]. The major benefit of W2W is the high manufacturing throughput and the ability to handle small dies. However, it suffers from low compound yield. In D2D a high yield can be obtained due to Known Good Die (KGD) stacking, but the throughput is expected to be low. The manufacturing throughput in D2W settles between D2D and W2W, and results in similar yields as in D2D due to the same ability of KGD stacking.