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Three dimensional chip stacking using a wafer-to-wafer integration 使用晶圆到晶圆集成的三维芯片堆叠
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382355
R. Chatterjee, M. Fayolle, P. Leduc, S. Pozder, B. Jones, E. Acosta, B. Charlet, T. Enot, M. Heitzmann, M. Zussy, A. Roman, O. Louveau, S. Maitrejean, D. Louis, N. Kernevez, N. Sillon, G. Passemard, V. Po, V. Mathew, S. Garcia, T. Sparks, Zhihong Huang
{"title":"Three dimensional chip stacking using a wafer-to-wafer integration","authors":"R. Chatterjee, M. Fayolle, P. Leduc, S. Pozder, B. Jones, E. Acosta, B. Charlet, T. Enot, M. Heitzmann, M. Zussy, A. Roman, O. Louveau, S. Maitrejean, D. Louis, N. Kernevez, N. Sillon, G. Passemard, V. Po, V. Mathew, S. Garcia, T. Sparks, Zhihong Huang","doi":"10.1109/IITC.2007.382355","DOIUrl":"https://doi.org/10.1109/IITC.2007.382355","url":null,"abstract":"A three-dimensional (3D) wafer-to-wafer integration technology has been developed using face-to-face dielectric wafer bonding, followed by wafer thinning and backside interconnect formation. The key technologies required for this integration include: reliable defect free direct dielectric wafer bonding, precise wafer-to-wafer alignment, backside thinning, deep inter-strata via (ISV) formation, and wafer patterning alignment across strata. Electrical measurements indicate continuity of ISV chains for all but the smallest vias.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126207207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Integration of High Performance and Low Cost Cu/Ultra Low-k SiOC(k=2.0) Interconnects with Self-formed Barrier Technology for 32nm-node and Beyond 高性能低成本Cu/超低k SiOC(k=2.0)互连与32nm及以上节点自形成势垒技术的集成
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382351
Y. Ohoka, Y. Ohba, A. Isobayashi, T. Hayashi, N. Komai, S. Arakawa, R. Kanamura, S. Kadomura
{"title":"Integration of High Performance and Low Cost Cu/Ultra Low-k SiOC(k=2.0) Interconnects with Self-formed Barrier Technology for 32nm-node and Beyond","authors":"Y. Ohoka, Y. Ohba, A. Isobayashi, T. Hayashi, N. Komai, S. Arakawa, R. Kanamura, S. Kadomura","doi":"10.1109/IITC.2007.382351","DOIUrl":"https://doi.org/10.1109/IITC.2007.382351","url":null,"abstract":"A method of integrating high performance and low-cost Cu ultra low-k (ULK) SiOC(k=2.0) hybrid interconnects with SiOC(k=2.65) hard mask structure has been developed. The method combines Cu/ULK interconnects with the self-formed MnOx barrier layer that was shown to have lower resistance and higher reliability than Cu alloys. Moreover, dual-damascene (DD) interconnects with MnOx barrier layer showed excellent stress-induced voiding performance and significantly longer electromigration lifetime and required no additional pore-sealing process. It is concluded that this self-formed barrier process is the most feasible technology for 32 nm-node Cu/ULK interconnects.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129303313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Impact of Cu microstructure on electromigration reliability Cu微观结构对电迁移可靠性的影响
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382357
C. Hu, L. Gignac, B. Baker, E. Liniger, R. Yu, P. Flaitz
{"title":"Impact of Cu microstructure on electromigration reliability","authors":"C. Hu, L. Gignac, B. Baker, E. Liniger, R. Yu, P. Flaitz","doi":"10.1109/IITC.2007.382357","DOIUrl":"https://doi.org/10.1109/IITC.2007.382357","url":null,"abstract":"The effect of Cu microstructure on electromigration (EM) has been investigated. A variation in the Cu grain size distributions between wafers was achieved by adjusting the wafer annealing process step after Cu electroplating and before Cu chemical mechanical polishing. Void growth morphology was observed by in-situ and ex-situ scanning electron microscope (SEM) techniques. The Cu lifetime and mass flow in samples with bamboo, near bamboo, bamboo-polycrystalline mixture, and polycrystalline grain structures were measured. The introduction of polycrystalline Cu line grain structure in fine lines for the 65 nm node technology and beyond markedly reduced the Cu EM reliability. The smaller Cu grain size distribution resulted in a shorter EM lifetime and a faster mass flow. The EM activation energies for Cu along Cu/amorphous a-SiCxNyHz interface and grain boundary were found to be 0.95 and 0.79 eV, respectively.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127998610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
Electrical Properties of Carbon Nanotube Via Interconnects Fabricated by Novel Damascene Process 新型Damascene工艺制备碳纳米管互连的电学性能
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382390
M. Nihei, T. Hyakushima, Shintaro Sato, T. Nozue, M. Norimatsu, Miho Mishima, T. Murakami, D. Kondo, A. Kawabata, M. Ohfuti, Y. Awano
{"title":"Electrical Properties of Carbon Nanotube Via Interconnects Fabricated by Novel Damascene Process","authors":"M. Nihei, T. Hyakushima, Shintaro Sato, T. Nozue, M. Norimatsu, Miho Mishima, T. Murakami, D. Kondo, A. Kawabata, M. Ohfuti, Y. Awano","doi":"10.1109/IITC.2007.382390","DOIUrl":"https://doi.org/10.1109/IITC.2007.382390","url":null,"abstract":"We studied the electrical properties of a carbon nanotube (CNT) via interconnect fabricated by a novel damascene process which is mostly compatible with conventional Cu interconnects. It was found that the resistance of 60-nm-height vias was independent of temperatures as high as 423 K, which suggests that the carrier transport is ballistic. The obtained resistance of 0.05 Omega for 2.8-mum-diameter vias is the lowest value ever reported. From the via height dependence of the resistance, the electron mean free path was estimated to be about 80 nm, which is similar to the via height predicted for 32-nm technology node (year 2013). This indicates that it will be possible to realize CNT vias with ballistic transport for 32-nm technology node and below.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117173854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
An alternative low resistance MOL technology with electroplated rhodium as contact plugs for 32nm CMOS and beyond 另一种低电阻MOL技术，采用电镀铑作为32nm及以上CMOS的触点插头
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382360
I. Shao, J. Cotte, B. Haran, Anna W. Topol, E. Simonyi, C. Cabral, H. Deligianni
{"title":"An alternative low resistance MOL technology with electroplated rhodium as contact plugs for 32nm CMOS and beyond","authors":"I. Shao, J. Cotte, B. Haran, Anna W. Topol, E. Simonyi, C. Cabral, H. Deligianni","doi":"10.1109/IITC.2007.382360","DOIUrl":"https://doi.org/10.1109/IITC.2007.382360","url":null,"abstract":"This paper addresses a critical CMOS challenge of increasing parasitic resistance by introducing electroplated rhodium (Rh) as an alternative middle-of-line (MOL) metallurgy to replace the conventional CVD tungsten (W) processes for lower contact resistance and better extendibility to 32 nm technology and beyond. Electroplating of Rh is shown to have similar to Cu superconformal filling capability, allowing us to successfully fill high aspect ratio vias (40 nm times 240 nm). Plating of 300 mm wafers with 60 nm times 290 nm vias was demonstrated using CVD or ALD ruthenium (Ru) as the seed layer. An annealing process was developed to obtain a thin Rh film resistivity of 6.5 muOmega-cm, which is 1.5 to 3X lower than the resistivity of CVD W films. Since Rh is stable in Si environment, when compared to a fast diffusing Cu, a very thin Ti/Ru layer can be implemented. Therefore we propose to use PVD Ti/ALD Ru/electroplated Rh as the alternative MOL metallurgy. With this simple liner/seed/fill stack, the overall MOL resistance is calculated to be 2x lower than the overall MOL resistance of the conventional W stacks, and slightly lower than Cu fill stacks. In addition, the ability to use a thinner liner layer than that used for Cu-base fill process, provides a greater potential for extendibility of Rh fill into future CMOS MOL generations.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"40 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132501698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Scaling of a Low Capacitance Highly Selective Self Aligned Contact Process 低电容高选择性自对准触点工艺的缩放
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382369
W. Graf, O. Genz, D. Kohler, H. Prenz, K. Schupke, A. Laessig, L. Bartholomaeus
{"title":"Scaling of a Low Capacitance Highly Selective Self Aligned Contact Process","authors":"W. Graf, O. Genz, D. Kohler, H. Prenz, K. Schupke, A. Laessig, L. Bartholomaeus","doi":"10.1109/IITC.2007.382369","DOIUrl":"https://doi.org/10.1109/IITC.2007.382369","url":null,"abstract":"A novel self aligned contact integration manufacturing method with oxide spacer is presented. Two main issues of conventional self aligned contacts are solved: high parasitic capacitive coupling through the nitride spacer and the small process window of the SAC etch. Parasitic coupling was reduced by 34 %. For the first time self aligned contacts with oxide spacer are used in DRAM production on 90 and 75 nm. The technology is seen to be extendible to 40 nm and below.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121689494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Densification of Carbon Nanotube Bundles for Interconnect Application 互连用碳纳米管束致密化研究
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382389
Z. Liu, N. Bajwa, L. Ci, S. Lee, S. Kar, P. Ajayan, J. Lu
{"title":"Densification of Carbon Nanotube Bundles for Interconnect Application","authors":"Z. Liu, N. Bajwa, L. Ci, S. Lee, S. Kar, P. Ajayan, J. Lu","doi":"10.1109/IITC.2007.382389","DOIUrl":"https://doi.org/10.1109/IITC.2007.382389","url":null,"abstract":"We demonstrated a post-growth processing method to increase the site density of carbon nanotube (CNT) bundles, a critical step towards CNT interconnect for use in future ICs. CVD-grown CNT bundles are immersed in an organic solvent, then withdrawn from the liquid bath by solvent evaporation, and consequently compacted. The CNT site density is increased 5~25 times. Influences of bundle structure parameters on densification are discussed and the interconnect implementation of densified CNTs is presented.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116633802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
45nm-node Interconnects with Porous SiOCH-Stacks, Tolerant of Low-Cost Packaging Applications 45nm节点与多孔sioch堆栈互连，适用于低成本封装应用
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382384
N. Inoue, M. Tagami, F. Itoh, H. Yamamoto, T. Takeuchi, S. Saito, N. Furutake, M. Ueki, M. Tada, T. Suzuki, Y. Hayashi
{"title":"45nm-node Interconnects with Porous SiOCH-Stacks, Tolerant of Low-Cost Packaging Applications","authors":"N. Inoue, M. Tagami, F. Itoh, H. Yamamoto, T. Takeuchi, S. Saito, N. Furutake, M. Ueki, M. Tada, T. Suzuki, Y. Hayashi","doi":"10.1109/IITC.2007.382384","DOIUrl":"https://doi.org/10.1109/IITC.2007.382384","url":null,"abstract":"The 45 nm-node interconnect with porous SiOCH-stacks of keff=2.9 is confirmed to have the practical reliability in PGBA and QFP. Adhesion strength of the via-ILD to the lower SiCN capping layer significantly impacts on the wire-bond reliability, but spreading the contact area of the bonding-wire within the fine-pitched bonding-pad suppresses the bonding failures in the low-k stack structures, irrespective of additional process of low-k curing or not. No failure was detected during reliability tests in PBGA package as well as QFP, confirming the practicality of the low keff interconnects for 45 nm-node ULSIs.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122780504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
CMOS Integration of Capacitive, Optical, and Electrical Interconnects 电容、光学和电气互连的CMOS集成
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382354
J. Lexau, Xuezhe Zheng, J. Bergey, A. Krishnamoorthy, R. Ho, R. Drost, J. Cunningham
{"title":"CMOS Integration of Capacitive, Optical, and Electrical Interconnects","authors":"J. Lexau, Xuezhe Zheng, J. Bergey, A. Krishnamoorthy, R. Ho, R. Drost, J. Cunningham","doi":"10.1109/IITC.2007.382354","DOIUrl":"https://doi.org/10.1109/IITC.2007.382354","url":null,"abstract":"We present a 90 nm test chip integrating proximity communication, optics using external lasers and photodiodes, and CML electronics on a single CMOS chip which can route data at multi-Gb/s rates through any combination of its three interconnect interfaces. A robust and flexible unclocked datapath allows independent timing and margin characterization of each path.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129034931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Experimental Determination of the Toughness of Crack Stop Structures 止裂结构韧性的实验测定
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382368
T. Shaw, E. Liniger, G. Bonilla, J. Doyle, B. Herbst, X. Liu, M. Lane
{"title":"Experimental Determination of the Toughness of Crack Stop Structures","authors":"T. Shaw, E. Liniger, G. Bonilla, J. Doyle, B. Herbst, X. Liu, M. Lane","doi":"10.1109/IITC.2007.382368","DOIUrl":"https://doi.org/10.1109/IITC.2007.382368","url":null,"abstract":"In this paper we present an experimental approach to the determining the toughness of crackstop structures. It is shown that methods used for adhesion testing can be adapted to quantitatively determine the effective toughness of different crackstop designs. A design based on metal pad shapes connected together with vias is shown to be capable of producing toughnesses that are 3.75 times the intrinsic toughness of the dielectric. In an optimized design we obtain a further 60% improvement in the crackstop toughness. The experiments presented provide an accurate way of determining the effectiveness of crackstop designs in arresting dicing flaws driven by the stresses present in different packages.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"161 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124625993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
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