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A Highly Reliable Cu Interconnect Technology for Memory Device 一种高可靠的存储器件铜互连技术
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382350
H. Lee, J. Hong, G. J. Seong, J. Lee, H. Park, J. Baek, K. Choi, B. Park, J. Bae, G. Choi, S. Kim, U. Chung, J. Moon, J. Oh, J. Son, J.H. Jung, S. Hah, S.Y. Lee
{"title":"A Highly Reliable Cu Interconnect Technology for Memory Device","authors":"H. Lee, J. Hong, G. J. Seong, J. Lee, H. Park, J. Baek, K. Choi, B. Park, J. Bae, G. Choi, S. Kim, U. Chung, J. Moon, J. Oh, J. Son, J.H. Jung, S. Hah, S.Y. Lee","doi":"10.1109/IITC.2007.382350","DOIUrl":"https://doi.org/10.1109/IITC.2007.382350","url":null,"abstract":"This paper describes the development of Cu interconnect technology for memory devices. A highly reliable sub 50 nm Cu interconnect lines were successfully fabricated by using optimized iPVD barrier/seed and electroplating process. The resistivity of Cu lines was reviewed with that of Al for extendibility of Cu. The Cu TDDB lifetime in user conditions was investigated to confirm the reliability of Cu process integration. It can be predicted that Cu metallization can satisfy the requirements of sub 50 nm trench pattern, which are lower resistance than Al and good reliabilities.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131729836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Robust integration of an ULK SiOCH dielectric (k=2.3) for high performance 32nm node BEOL 用于高性能32nm节点BEOL的ULK SiOCH电介质(k=2.3)的鲁棒集成
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382382
M. Aimadeddine, V. Jousseaume, V. Amal, L. Favennec, A. Farcy, A. Zenasni, M. Assous, M. Vilmay, S. Jullian, P. Maury, V. Delaye, N. Jourdan, T. Vanypre, P. Brun, G. Imbert, Y. Lefriec, M. Mellier, H. Chaabouni, L. Chapelon, K. Hamioud, F. Volpi, D. Louis, G. Passemard, J. Torres
{"title":"Robust integration of an ULK SiOCH dielectric (k=2.3) for high performance 32nm node BEOL","authors":"M. Aimadeddine, V. Jousseaume, V. Amal, L. Favennec, A. Farcy, A. Zenasni, M. Assous, M. Vilmay, S. Jullian, P. Maury, V. Delaye, N. Jourdan, T. Vanypre, P. Brun, G. Imbert, Y. Lefriec, M. Mellier, H. Chaabouni, L. Chapelon, K. Hamioud, F. Volpi, D. Louis, G. Passemard, J. Torres","doi":"10.1109/IITC.2007.382382","DOIUrl":"https://doi.org/10.1109/IITC.2007.382382","url":null,"abstract":"An Ultra Low-K (ULK) SiOCH porous dielectric with k=2.3 targeted for the 32 nm node is integrated at local and intermediate levels with the Trench First Hard Mask architecture currently implemented for the 65/45 nm nodes. Physical and electrical characterizations after integration show good barrier integrity, substantial gain in capacitance as well as good via chain functionality. The material exhibits similar interline leakage and breakdown field than the k=2.5 reference dielectric meeting specifications of the 32 nm node.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115904527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Assessing the Effect of Die Sealing in Cu/Low-k Structures 铜/低钾结构中模具密封效果的评估
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382363
A. Kearney, A. V. Vairagar, H. Geisler, E. Zschech, R. Dauskardt
{"title":"Assessing the Effect of Die Sealing in Cu/Low-k Structures","authors":"A. Kearney, A. V. Vairagar, H. Geisler, E. Zschech, R. Dauskardt","doi":"10.1109/IITC.2007.382363","DOIUrl":"https://doi.org/10.1109/IITC.2007.382363","url":null,"abstract":"The integration of porous low-k dielectric materials in backend structures in microelectronics has presented numerous processing and reliability challenges, as their porous structure make them mechanically weaker than the fully dense materials they have replaced. Sawing of the wafer into individual die can nucleate cracking along the perimeter which can propagate to reduce device yield and significantly impact the interconnect structure. Die sealing structures have been shown to substantially increase the fracture and damage resistance of the interconnect structure. In this study, we describe fracture mechanics methods using both monotonic and cyclic fatigue loading to assess the effects of die seal structures.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116979378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Mechanism and Application of Negative Charging Mode of Electron Beam Inspection for PMOS Leakage Detection 电子束负电荷模式检测PMOS漏电的机理及应用
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382362
Li-Lung Lai, Keren Xu, D. Deng, J. Ning, Hong Xiao, Yan Zhao, E. Ma, J. Jau
{"title":"Mechanism and Application of Negative Charging Mode of Electron Beam Inspection for PMOS Leakage Detection","authors":"Li-Lung Lai, Keren Xu, D. Deng, J. Ning, Hong Xiao, Yan Zhao, E. Ma, J. Jau","doi":"10.1109/IITC.2007.382362","DOIUrl":"https://doi.org/10.1109/IITC.2007.382362","url":null,"abstract":"In this study, we modified surface condition of tungsten chemical mechanical polish (WCMP) to resolve the mix mode issue and achieved and optimized negative mode electron beam inspection (EBI). We detected dark voltage contrast (DVC) defects on static random access memory (SRAM) array at PMOS contacts. Physical failure analysis (PFA) results confirmed prediction that they are P+/N-well junction leakages caused by nickel silicide (NiSix) spiking.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"54 87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126900493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability BEOL工艺与Cu/FSG布线在90 nm设计规则DDR DRAM的集成及其对良率、刷新时间和晶圆级可靠性的影响
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382367
N. Kwak, Sang-Tae Ahn, Hyung-Soon Park, Seomin Kim, Jin-Ki Jung, G. Kim, Geunho Choi, Dong-Chul Koo, Tae-Oh Jung, J. Ku, Jae-Kwan Jung, Jinwoong Kim, Sungwook Park, H. Sohn, Soo-Hyun Kim
{"title":"BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability","authors":"N. Kwak, Sang-Tae Ahn, Hyung-Soon Park, Seomin Kim, Jin-Ki Jung, G. Kim, Geunho Choi, Dong-Chul Koo, Tae-Oh Jung, J. Ku, Jae-Kwan Jung, Jinwoong Kim, Sungwook Park, H. Sohn, Soo-Hyun Kim","doi":"10.1109/IITC.2007.382367","DOIUrl":"https://doi.org/10.1109/IITC.2007.382367","url":null,"abstract":"For the first time, this paper presents the results of successful integrations of Cu wiring into a production 512 Mb/90 nm design-rule stacked capacitor and recessed gate DDR (double data rate) DRAM technology, focusing on the effects of Cu integration on DRAM performance, yield, refresh time, and wafer-level reliability. 2 levels Cu interconnect (Ml single damascene and M2 dual damascene) and CVD low-k (FSG) materials have been implemented. Both the reduction in parasitic capacitance and line resistance were found to improve the operation speed of DRAM. No degradation was observed in view of normalized refresh time and yield with Cu wiring. The reliability issues with Cu integration to DRAM were systematically evaluated. In conclusion, this study demonstrates that the Cu wiring is fully compatible with the conventional DRAM and will be expected to meet the requirements of high-performance and high-speed advanced DRAM beyond sub-50 nm node.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125667767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design for Manufacturability in Backend Reliability and Packaging of Nanoscale Technologies 纳米技术后端可靠性和封装中的可制造性设计
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382342
Y. K. Lim, J.B. Tan, K. Pey, E. Chua, Y. H. Yeo, T. Fu, L. Hsia
{"title":"Design for Manufacturability in Backend Reliability and Packaging of Nanoscale Technologies","authors":"Y. K. Lim, J.B. Tan, K. Pey, E. Chua, Y. H. Yeo, T. Fu, L. Hsia","doi":"10.1109/IITC.2007.382342","DOIUrl":"https://doi.org/10.1109/IITC.2007.382342","url":null,"abstract":"Integration of copper (Cu) and low-k dielectrics has posed significant challenges for device reliability and packaging. For faster and successful semiconductor product introduction, early implementation of simulation model for physics and mechanical studies, and the subsequent design for manufacturability (DFM) are important considerations for device reliability and packaging communities. In this paper, several structural designs and finite element analysis (FEA) simulation models were employed to illustrate the importance of DFM in backend reliability and packaging. Also, its extendibility to future nanoscale technologies employing porous ultra low-k Cu interconnects was discussed.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132651389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimizing ALD WN Process for 65nm Node CMOS Contact Application 65纳米节点CMOS触点应用ALD WN工艺优化
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382361
Y. Chen, T. Hung, Y. Chang, K. Shieh, C. Hsu, C. Huang, W.H. Yan, K. Ashtiani, D. Pisharoty, W. Lei, S. Chang, F. Huang, J. Collins, S. F. Tzou
{"title":"Optimizing ALD WN Process for 65nm Node CMOS Contact Application","authors":"Y. Chen, T. Hung, Y. Chang, K. Shieh, C. Hsu, C. Huang, W.H. Yan, K. Ashtiani, D. Pisharoty, W. Lei, S. Chang, F. Huang, J. Collins, S. F. Tzou","doi":"10.1109/IITC.2007.382361","DOIUrl":"https://doi.org/10.1109/IITC.2007.382361","url":null,"abstract":"ALD tungsten nitride (WN) becomes attractive for CMOS contact liner/barrier application because of its highly conductive and conformal film properties. Due to the distinct differences in its process nature from the traditional PVD processes, a full optimization from film properties to process integration is necessary for the 65 nm CMOS device fabrication. This paper highlights the issues and shows the approaches to address these issues in implementing the ALD WN process for the CMOS contact application.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134408561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Progress of 3D Integration Technologies and 3D Interconnects 三维集成技术与三维互联进展
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382393
S. Pozder, R. Chatterjee, A. Jain, Zhihong Huang, R.E. Jones, E. Acosta
{"title":"Progress of 3D Integration Technologies and 3D Interconnects","authors":"S. Pozder, R. Chatterjee, A. Jain, Zhihong Huang, R.E. Jones, E. Acosta","doi":"10.1109/IITC.2007.382393","DOIUrl":"https://doi.org/10.1109/IITC.2007.382393","url":null,"abstract":"Three dimensional stacked circuits having multiple active semiconductor levels rely on the development of strata bonding, micro connects between strata, through strata vias (TSV) and a wafer thinning process. Progress in the each of these process technologies for 3D strata stacking is opening the path to more robust and capable 3D process integrations.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123860783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
Stress and Slurry Chemistry Effects on CMP Damage of Ultra-Low-k Dielectrics 应力和浆料化学对超低k电介质CMP损伤的影响
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382373
Taek‐Soo Kim, Qiping Zhong, M. Peterson, H. Tarn, T. Konno, R. Dauskardt
{"title":"Stress and Slurry Chemistry Effects on CMP Damage of Ultra-Low-k Dielectrics","authors":"Taek‐Soo Kim, Qiping Zhong, M. Peterson, H. Tarn, T. Konno, R. Dauskardt","doi":"10.1109/IITC.2007.382373","DOIUrl":"https://doi.org/10.1109/IITC.2007.382373","url":null,"abstract":"The yield and reliability of the next generation Cu/low-k interconnects depends critically on the control of damage in the form of crack growth in ultra-low-k (ULK) dielectrics. The ULK dielectrics are mechanically fragile and susceptible to environmentally accelerated cracking in reactive aqueous environments. Nevertheless, during chemical mechanical planarization (CMP) and post-CMP cleaning these extremely brittle thin-film structures are subjected to mechanical loads in the presence of harsh aqueous solutions. We demonstrate that both process stress and chemistry are crucial for the rate of damage evolution during CMP. Small changes in CMP slurry chemistry and surfactant additions can have a dramatic effect on damage processes and associated CMP yield. These are crucial aspects for the reliable integration of ultra-low-k materials at next technology nodes.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126180154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Mechanistic Study of Plasma Damage and CH4 Recovery of Low k Dielectric Surface 低k介质表面等离子体损伤与CH4恢复机理研究
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382366
J. Bao, H.L. Shi, J. Liu, H. Huang, P. Ho, M. D. Goodner, M. Moinpour, G. Kloster
{"title":"Mechanistic Study of Plasma Damage and CH4 Recovery of Low k Dielectric Surface","authors":"J. Bao, H.L. Shi, J. Liu, H. Huang, P. Ho, M. D. Goodner, M. Moinpour, G. Kloster","doi":"10.1109/IITC.2007.382366","DOIUrl":"https://doi.org/10.1109/IITC.2007.382366","url":null,"abstract":"A mechanistic study was performed to investigate plasma damage and CFL, recovery of porous carbon-doped oxide (CDO) low k surfaces. First the nature of damage was examined for different plasma treatments in a standard RIE chamber then followed by a study using a downstream hybrid plasma source with separate ions and atomic radicals to investigate their respective roles in the plasma process. Plasma damage was found to be a complicated phenomenon involving both chemical and physical effects, depending on chemical reactivity and the energy and mass of the plasma species. Moisture uptake after plasma damage was found to be a major reason to cause dielectric constant increase. The CFL plasma treatment was found to be promising in repairing oxygen ashing damages by formation of a carbon-rich polymer layer. However, sp2 carbons on the top polymer layer seemed to limit the penetration of plasma CH4 and thus full recovery of low k damage.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130458178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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