M. Aimadeddine, V. Jousseaume, V. Amal, L. Favennec, A. Farcy, A. Zenasni, M. Assous, M. Vilmay, S. Jullian, P. Maury, V. Delaye, N. Jourdan, T. Vanypre, P. Brun, G. Imbert, Y. Lefriec, M. Mellier, H. Chaabouni, L. Chapelon, K. Hamioud, F. Volpi, D. Louis, G. Passemard, J. Torres
{"title":"Robust integration of an ULK SiOCH dielectric (k=2.3) for high performance 32nm node BEOL","authors":"M. Aimadeddine, V. Jousseaume, V. Amal, L. Favennec, A. Farcy, A. Zenasni, M. Assous, M. Vilmay, S. Jullian, P. Maury, V. Delaye, N. Jourdan, T. Vanypre, P. Brun, G. Imbert, Y. Lefriec, M. Mellier, H. Chaabouni, L. Chapelon, K. Hamioud, F. Volpi, D. Louis, G. Passemard, J. Torres","doi":"10.1109/IITC.2007.382382","DOIUrl":null,"url":null,"abstract":"An Ultra Low-K (ULK) SiOCH porous dielectric with k=2.3 targeted for the 32 nm node is integrated at local and intermediate levels with the Trench First Hard Mask architecture currently implemented for the 65/45 nm nodes. Physical and electrical characterizations after integration show good barrier integrity, substantial gain in capacitance as well as good via chain functionality. The material exhibits similar interline leakage and breakdown field than the k=2.5 reference dielectric meeting specifications of the 32 nm node.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"155 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE International Interconnect Technology Conferencee","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2007.382382","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
An Ultra Low-K (ULK) SiOCH porous dielectric with k=2.3 targeted for the 32 nm node is integrated at local and intermediate levels with the Trench First Hard Mask architecture currently implemented for the 65/45 nm nodes. Physical and electrical characterizations after integration show good barrier integrity, substantial gain in capacitance as well as good via chain functionality. The material exhibits similar interline leakage and breakdown field than the k=2.5 reference dielectric meeting specifications of the 32 nm node.