2007 IEEE International Interconnect Technology Conferencee最新文献

Highly-oriented PVD Ruthenium Liner for Low-resistance Direct-plated Cu Interconnects 用于低电阻直接镀铜互连的高取向PVD钌衬垫

2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382331

M. Abe, M. Ueki, M. Tada, T. Onodera, N. Furutake, K. Shimura, S. Saito, Y. Hayashi

引用次数: 10

Chip Package Interaction for 65nm CMOS Technology with C4 Interconnections 采用C4互连的65nm CMOS技术的芯片封装交互

2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382388

M. Farooq, I. Melville, C. Muzzy, P. Mclaughlin, R. Hannon, W. Sauter, J. Muncy, D. Questad, C. Carey, M. Cullinan-Scholl, V. McGahay, M. Angyal, H. Nye, M. Lane, X. H. Liu, T. Shaw, C. Murray

引用次数: 5

Balancing Resistance and Capacitance of Signal Interconnects for Power Saving 平衡信号互连的电阻和电容以节省电力

2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382372

V. Hoang, G. Doornbos, J. Michelon, A. Kumar, A. Nackaerts, P. Christie

{"title":"Balancing Resistance and Capacitance of Signal Interconnects for Power Saving","authors":"V. Hoang, G. Doornbos, J. Michelon, A. Kumar, A. Nackaerts, P. Christie","doi":"10.1109/IITC.2007.382372","DOIUrl":"https://doi.org/10.1109/IITC.2007.382372","url":null,"abstract":"This paper presents the results of a study on the trade-off between resistance and capacitance of signal interconnects in a low-power circuit to further reduce power consumption without sacrificing speed performance. Simulation and experimental results show that by simply thinning down the interconnect height by half; the power consumption and frequency of a test interconnect-loaded ring- oscillator are improved by 12.7% and 3.5%, respectively. The combination of thin-interconnect with low-operational-power (LOP) transistors, which are designed to have low threshold voltage and to operate at lower supply voltage, results in a 50% reduction in power consumption without penalty in frequency. By thinning down the interconnect height, the RC time constant of the interconnect is increased. However, this increment does not have negative impact on circuit performance until the length of interconnect is above few hundred micrometers. This indicates thin interconnect is suitable for intermediate interconnect levels where the majority of shorter interconnects are located. Reliability study of thin-interconnect shows no sign of electro-migration resistance degradation. Furthermore, only a small impact of process variations on timing of a critical path, which uses thin-interconnects, was observed.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127704370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Chip-Package-Interaction Modeling of Ultra Low-k/Copper Back End of Line 超低k/铜后端线路的芯片-封装相互作用建模

2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382334

X. Liu, T. Shaw, M. Lane, E. Liniger, B. Herbst, D. Questad

引用次数: 52

The influence of the size effect of copper interconnects on RC delay variability beyond 45nm technology 铜互连的尺寸效应对超过45nm技术的RC延迟变化的影响

2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382333

H. Kitada, T. Suzuki, T. Kimura, H. Kudo, H. Ochimizu, S. Okano, A. Tsukune, S. Suda, S. Sakai, N. Ohtsuka, T. Tabira, T. Shirasu, M. Sakamoto, A. Matsuura, Y. Asada, T. Nakamura

{"title":"The influence of the size effect of copper interconnects on RC delay variability beyond 45nm technology","authors":"H. Kitada, T. Suzuki, T. Kimura, H. Kudo, H. Ochimizu, S. Okano, A. Tsukune, S. Suda, S. Sakai, N. Ohtsuka, T. Tabira, T. Shirasu, M. Sakamoto, A. Matsuura, Y. Asada, T. Nakamura","doi":"10.1109/IITC.2007.382333","DOIUrl":"https://doi.org/10.1109/IITC.2007.382333","url":null,"abstract":"We tried to evaluate and predict the RC delay variability beyond the 45 nm copper interconnects technologies. The RC delay variability as a normalized delay time distribution, is caused by the line width/height variations due to the manufacturing process fluctuations. In order to evaluate the influence of the resistivity size effect precisely, we improved Fuchs-Sondheimer (F-S) and Mayadas-Shatzkes (M-S) models, in order to include the line height dependence of copper grain size, and applied it in the evaluation of the RC delay variability based on the SPICE simulation. In our results, we found that the RC delay variability in the 45nm node technology was relatively small, weakly dependent on the grid size and line height, and almost not affected by the size effect. On the contrary, in the 32 nm technology, the RC delay variability was about 2 times larger than the case ignoring the size effect and reached to the 20% of the average delay time at 3000 grid with 10% of line size fluctuation. In the 32 nm technology, the line height dependence of the RC delay variability was also strong and increased with decreasing line height. The influence of line height dependence of grain size reached about 1/5 or more of the total size effect in the RC delay variability.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132852510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Electromigration Failure Mechanism and Lifetime Expectation for Bi-Modal Distribution in Cu/Low-k Interconnect 铜/低钾互连中双模态分布的电迁移失效机制和寿命预期

2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382343

Y. Wee, A. Kim, Jung-Eun Lee, J. Maeng, W. Choi, S.W. Nam, Seung-jin Lee, Kyoung-Woo Lee, Jae-Hak Kim, K. Jun, Seungwook Choi, Jaeouk Choo, J. Heo, Hong-jae Shin, N. Lee

引用次数: 4

A comparative study of thermal and plasma enhanced ALD Ta-N-C films on SiO2, SiCOH and Cu substrates 在SiO2, SiCOH和Cu基底上热和等离子体增强ALD Ta-N-C薄膜的比较研究

2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382335

H. Wojcik, M. Friedemann, F. Feustelt, M. Albert, S. Ohsiekt, J. Metzgert, J. Voss, J. Bartha, C. Wenze

{"title":"A comparative study of thermal and plasma enhanced ALD Ta-N-C films on SiO2, SiCOH and Cu substrates","authors":"H. Wojcik, M. Friedemann, F. Feustelt, M. Albert, S. Ohsiekt, J. Metzgert, J. Voss, J. Bartha, C. Wenze","doi":"10.1109/IITC.2007.382335","DOIUrl":"https://doi.org/10.1109/IITC.2007.382335","url":null,"abstract":"Thermal and plasma enhanced atomic layer deposition (ALD) of tantalum nitride (TaN) thin films have been performed using PDMAT and NH3, and TBTDET in combination with hydrogen radicals and argon ions, respectively. The films were grown on SiO2, SiCOH and Cu, to study the influence of diverse kinds of substrates on growth behaviour and properties of ultra thin TaN layers. X-ray reflectometry (XRR), transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) were used to characterize these films. Their step coverage in 65 nm technology test structures and Cu diffusion into bare Si- wafers were also investigated. In the case of thermal ALD resulting non-metallic Ta-N-C films show good growth behaviour on SiO2 and Cu, but some difficulties were revealed on SiCOH. Contrary, the use of plasma led to Ta-C-N films on all three substrates. They are rather tantalum carbide in nature and possess resistivities of less than 300 muOmegacm. A 1 nm PEALD barrier proved to be stable against Cu diffusion during a 30 min anneal at 400degC.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"72 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129680505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Line Edge Roughness of Metal Lines and Time-Dependent Dielectric Breakdown Characteristics of Low-k Interconnect Dielectrics 金属线边缘粗糙度和低k互连介质的时间相关介电击穿特性

2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382376

A. Kim, T. Jeong, Miji Lee, Y.J. Moon, Seyoung Lee, Bong-heon Lee, Hyungoo Jeon

引用次数: 11

Development of an Eco-friendly Copper Interconnect Cleaning Process 一种环保铜互连清洗工艺的开发

2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382341

Y. Uozumi, T. Nakajima, T. Matsumura, Y. Yoshimizu, H. Tomita

引用次数: 1

Capacitance reduction effect using capping-layer removal process for porous low-k (k=2.5)/Cu system toward 45nm technology node 多孔低k (k=2.5)/Cu体系在45nm工艺节点上的电容降低效应

2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382365

N. Ohashi, E. Soda, T. Suzuki, S. Kondo, N. Oda, S. Ogawa, S. Saito

引用次数: 0