M. Farooq, I. Melville, C. Muzzy, P. Mclaughlin, R. Hannon, W. Sauter, J. Muncy, D. Questad, C. Carey, M. Cullinan-Scholl, V. McGahay, M. Angyal, H. Nye, M. Lane, X. H. Liu, T. Shaw, C. Murray
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Chip Package Interaction for 65nm CMOS Technology with C4 Interconnections
This paper discusses the chip package interaction (CPI) for a 65 nm low k BEOL CMOS chip assembled to an organic package. Inter-level dielectrics with k~3.0 and k~2.7, with oxide terminations, were used in combination with both Sn/Pb and lead-free C4s. Various underfill compounds were tested to determine their effectiveness in mitigating chip stresses without significantly impairing C4 fatigue life. A summary of the reliability stress results will be presented.
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