Capacitance reduction effect using capping-layer removal process for porous low-k (k=2.5)/Cu system toward 45nm technology node

Abstract

The Cu interconnects with porous SiOC-CVD (=p-SiOC, k=2.5) was successfully integrated into 45 nm technology node featuring an effective k-value (=k-eff) decreasing process. The decrease in k-eff was achieved by removing the capping layer on p-SiOC film and the damaged interface layer in p-SiOC using dry-etching process. Using this capping layer dry-etching process (=CEP), a 10% reduction in k-eff and a highly improved line-to-line leakage as well as longer TDDB lifetime are obtained for 45 nm technology node with 140 nm pitch metallization.