Balancing Resistance and Capacitance of Signal Interconnects for Power Saving

Abstract

This paper presents the results of a study on the trade-off between resistance and capacitance of signal interconnects in a low-power circuit to further reduce power consumption without sacrificing speed performance. Simulation and experimental results show that by simply thinning down the interconnect height by half; the power consumption and frequency of a test interconnect-loaded ring- oscillator are improved by 12.7% and 3.5%, respectively. The combination of thin-interconnect with low-operational-power (LOP) transistors, which are designed to have low threshold voltage and to operate at lower supply voltage, results in a 50% reduction in power consumption without penalty in frequency. By thinning down the interconnect height, the RC time constant of the interconnect is increased. However, this increment does not have negative impact on circuit performance until the length of interconnect is above few hundred micrometers. This indicates thin interconnect is suitable for intermediate interconnect levels where the majority of shorter interconnects are located. Reliability study of thin-interconnect shows no sign of electro-migration resistance degradation. Furthermore, only a small impact of process variations on timing of a critical path, which uses thin-interconnects, was observed.