Chip-Package-Interaction Modeling of Ultra Low-k/Copper Back End of Line

Abstract

Ultra low-k (ULK, k=2.4) dielectric has weaker mechanical properties than first generation low-k films (k=3.0). The introduction of ULK into advanced back end of lines (BEOL) presents a significant challenge due to chip package interaction (CPI) where the packaged die is cycled over a temperature range and the resulting stress can cause ULK BEOL delamination. To avoid CPI failure detailed modeling from the package down to the BEOL must be coupled with quantitative material property measurement. In this paper multi-level finite element models have been used to investigate the parameters which drive CPI failure. It is found that the defect size in the BEOL and the package geometry are key drivers for delamination. Finally, this paper presents a detailed example of the utility of modeling to optimize dicing to reduce defect size, and provide targets for crackstop toughness, which has resulted in a successful reliability qualification of the porous SiCOH (k=2.4) for 45 nm BEOL technology with an organic flip-chip package.