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Reliability of Cu Interconnects with Ta Implant Cu与Ta植入物互连的可靠性
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382340
J. Gambino, T. Sullivan, F. Chen, J. Gill, S. Mongeon, E. Adams, J. Burnham, K. Rodbell
{"title":"Reliability of Cu Interconnects with Ta Implant","authors":"J. Gambino, T. Sullivan, F. Chen, J. Gill, S. Mongeon, E. Adams, J. Burnham, K. Rodbell","doi":"10.1109/IITC.2007.382340","DOIUrl":"https://doi.org/10.1109/IITC.2007.382340","url":null,"abstract":"In this study, a novel method is explored for improving the electromigration lifetime of Cu wires, using a blanket Ta implantation into both the oxide and Cu on the surface of a wafer. For the highest implant dose, the electromigration lifetime is improved by over 5X using this method, with a minimal increase in wire resistance. An increase in lifetime is achieved, even for an average surface concentration of Ta on the order of 0.1 atm%. The line-to-line leakage at high voltages (> 5 V) increases with the Ta implant, with higher leakage at higher Ta concentrations. The lifetime for time dependent dielectric breakdown (TDDB) is significantly degraded for high Ta doses, but not for lower Ta doses, suggesting that there may be a window for improving electromigration lifetime while maintaining high dielectric reliability.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131484441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Cu / Barrier Metal Stack Film Characterization for Reliability Estimation 用于可靠性估计的铜/障碍金属堆叠薄膜表征
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382339
S. Ogawa, T. Ohdaira, N. Hosoi, N. Tarumi, R. Suzuki, S. Saito
{"title":"Cu / Barrier Metal Stack Film Characterization for Reliability Estimation","authors":"S. Ogawa, T. Ohdaira, N. Hosoi, N. Tarumi, R. Suzuki, S. Saito","doi":"10.1109/IITC.2007.382339","DOIUrl":"https://doi.org/10.1109/IITC.2007.382339","url":null,"abstract":"Elapsed time change in sheet resistance (SR) of Cu/barrier metal stacks have been evaluated correlated with behaviors of vacancies in Cu films at Cu/barrier interface areas (Cu barrier interfaces) by a positron-annihilation lifetime spectroscopy (PALS), and it was shown that the elapsed time change in SR strongly related to positron mean lifetime, namely vacancy clusters size, and those film properties showed a reasonable correlation with a reported SIV characteristics.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134117980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Simultaneous Cu-Cu and Compliant Dielectric Bonding for 3D Stacking of ICs 同时Cu-Cu和柔性介质键合用于集成电路的三维堆叠
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382391
A. Jourdain, S. Stoukatch, P. de Moor, W. Ruythooren
{"title":"Simultaneous Cu-Cu and Compliant Dielectric Bonding for 3D Stacking of ICs","authors":"A. Jourdain, S. Stoukatch, P. de Moor, W. Ruythooren","doi":"10.1109/IITC.2007.382391","DOIUrl":"https://doi.org/10.1109/IITC.2007.382391","url":null,"abstract":"This paper, for the first time reports the 3D stacking and interconnection of an extremely thinned IC by simultaneous Cu-Cu thermocompression and compliant glue layer bonding. Inclusion of a compliant glue layer serves reinforcement of the mechanical stability of the stack in areas where the inter-die interconnect density is low. It also enables separation in time of stacking on one hand and bonding on the other hand, thus enabling collective bonding after die to wafer stacking. We demonstrate electrically yielding 10 k through-wafer via chains without observable impact of the dielectric glue layer on the via chain resistance.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133387684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
The Development of an Innovative Process of Large Grained and Low Resistivity Cu Wires for less than hp 45nm ULSI 用于小于45nm超细硅的大晶粒低电阻率铜线创新工艺的开发
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382337
S. Tashiro, K. Khoo, T. Nagano, J. Onuki, Y. Chonan, H. Akahoshi, T. Tobita, M. Chiba, K. Ishikawa, N. Ishikawa
{"title":"The Development of an Innovative Process of Large Grained and Low Resistivity Cu Wires for less than hp 45nm ULSI","authors":"S. Tashiro, K. Khoo, T. Nagano, J. Onuki, Y. Chonan, H. Akahoshi, T. Tobita, M. Chiba, K. Ishikawa, N. Ishikawa","doi":"10.1109/IITC.2007.382337","DOIUrl":"https://doi.org/10.1109/IITC.2007.382337","url":null,"abstract":"We have developed an innovative process to create large grained and low resistivity Cu wires for less than hp 45 nm ULSIs. The resistivity of the 50 nm wide Cu wires by an innovative high purity process is found to be 21% lower than those created by the conventional process. It was also found that Cu wires formed with the new high purity process have larger grains with a smaller spread and a lower impurity concentration than those made with the conventional process. This innovative new process is expected to be a powerful candidate for created Cu wire of less than hp 45 nm ULSIs.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116741909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Extremely Low Keff (1.9) Cu Interconnects with Air Gap Formed Using SiOC 极低Keff (1.9) Cu互连与使用SiOC形成的气隙
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382364
T. Harada, A. Ueki, K. Tomita, K. Hashimoto, J. Shibata, H. Okamura, K. Yoshikawa, T. Iseki, M. Higashi, S. Maejima, K. Nomura, K. Goto, T. Shono, S. Muranaka, N. Torazawa, S. Hirao, M. Matsumoto, T. Sasaki, S. Matsumoto, S. Ogawa, M. Fujisawa, A. Ishii, M. Matsuura, T. Ueda
{"title":"Extremely Low Keff (1.9) Cu Interconnects with Air Gap Formed Using SiOC","authors":"T. Harada, A. Ueki, K. Tomita, K. Hashimoto, J. Shibata, H. Okamura, K. Yoshikawa, T. Iseki, M. Higashi, S. Maejima, K. Nomura, K. Goto, T. Shono, S. Muranaka, N. Torazawa, S. Hirao, M. Matsumoto, T. Sasaki, S. Matsumoto, S. Ogawa, M. Fujisawa, A. Ishii, M. Matsuura, T. Ueda","doi":"10.1109/IITC.2007.382364","DOIUrl":"https://doi.org/10.1109/IITC.2007.382364","url":null,"abstract":"Dual damascene Cu interconnects with Keff below 2.0 have been demonstrated for the first time. Air gaps between Cu lines were formed with a low K SiOC film in a carefully designed manner. CoWP cap layers were introduced to protect the Cu lines and to eliminate a dielectric liner layer. In addition, AGE (Air Gap Exclusion) was applied to solve crucial problems related to the air gaps. Keff of 1.9 was obtained at 65 nm design rule, which surpassed by far ITRS target (2.5~2.8) for hp 45. It was also confirmed that leakage current between lines was suppressed by the formation of the air gaps.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123224265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Toward a real system integration; A direction of IC technology 走向真正的系统集成;集成电路技术的一个方向
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382353
A. Matsuzawa
{"title":"Toward a real system integration; A direction of IC technology","authors":"A. Matsuzawa","doi":"10.1109/IITC.2007.382353","DOIUrl":"https://doi.org/10.1109/IITC.2007.382353","url":null,"abstract":"A direction of IC technology is discussed with relation to mixed signal and interconnects technology for realizing real system integration. IC technology has progressed from an integration of simple digital circuits to an integration of increasingly complicated circuits and devices. Mixed signal technology is currently widely used for SoCs to compensate damage of externally received signals. In CMOS RF circuit technology coping with the size of on-chip inductor technology is vital for many SoCs for wireless systems. Millimeter wave communication will realize Giga-bit wireless data transfer and requires interesting new IC technologies such as a transmission line and an on-chip antenna technology. Transmission of electric power to chips will be an important future IC technology for fine-grained power management systems and ubiquitous systems.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131364974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Chemical and Plasma Oxidation Behaviors of NiSi and NiPtSi Salicide Films in 65nm Node CMOS Process NiSi和NiPtSi盐化膜在65nm节点CMOS工艺中的化学和等离子体氧化行为
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382359
Yu-Lan Chang, Yi-Wei Chen, Yi-Cheng Chen, K. Shieh, Climbing Huang, S. F. Tzou
{"title":"Chemical and Plasma Oxidation Behaviors of NiSi and NiPtSi Salicide Films in 65nm Node CMOS Process","authors":"Yu-Lan Chang, Yi-Wei Chen, Yi-Cheng Chen, K. Shieh, Climbing Huang, S. F. Tzou","doi":"10.1109/IITC.2007.382359","DOIUrl":"https://doi.org/10.1109/IITC.2007.382359","url":null,"abstract":"The chemical and plasma oxidation behaviors of NiSi and NiPtSi salicide films in a 65 nm node CMOS device fabrication process have been investigated. By incorporating Pt into the nickel salicide formation process, the oxidation rate can be effectively reduced during both salicidation etch/clean and contact plasma etch processes. Data collected from this study suggests both stronger chemical bonding from PtSi and the aggregation of Pt near film surface attribute to this good oxidation resistance property.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131366959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Formation of Ni(Pt) Germanosilicide Using a Sacrificial Si Cap Layer 牺牲硅帽层制备Ni(Pt)锗硅化物
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382345
Yi-Wei Chen, Yu-Lan Chang, Yi-Cheng Chen, K. Shieh, Climbing Huang, S. F. Tzou
{"title":"Formation of Ni(Pt) Germanosilicide Using a Sacrificial Si Cap Layer","authors":"Yi-Wei Chen, Yu-Lan Chang, Yi-Cheng Chen, K. Shieh, Climbing Huang, S. F. Tzou","doi":"10.1109/IITC.2007.382345","DOIUrl":"https://doi.org/10.1109/IITC.2007.382345","url":null,"abstract":"Ni(Pt) alloy has been implemented in the SiGe silicidation process for 65nm node CMOS device fabrication. A thin Si cap layer was introduced into the in-situ doped Si1-xGexB film stack to further enhance the thermal stability of the silicide film. The Ni(Pt) germanosilicide temperature transition curves have been studied, N-/P-FET mismatch issues have been resolved, and a robust integration flow has been developed for the 65 nm node CMOS device fabrication.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116445451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Full Copper Electrochemical Mechanical Planarization (Ecmp) as a Technology Enabler for the 45 and 32nm Nodes 全铜电化学机械平面化(Ecmp)作为45和32nm节点的技术推动者
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382352
M. Mellier, T. Berger, R. Duru, M. Zaleski, M. C. Luche, M. Rivoire, C. Goldberg, G. Wyborn, K.-L. Chang, Y. Wang, V. Ripoche, S. Tsai, M. Thothadri, W. Hsu, L. Chen
{"title":"Full Copper Electrochemical Mechanical Planarization (Ecmp) as a Technology Enabler for the 45 and 32nm Nodes","authors":"M. Mellier, T. Berger, R. Duru, M. Zaleski, M. C. Luche, M. Rivoire, C. Goldberg, G. Wyborn, K.-L. Chang, Y. Wang, V. Ripoche, S. Tsai, M. Thothadri, W. Hsu, L. Chen","doi":"10.1109/IITC.2007.382352","DOIUrl":"https://doi.org/10.1109/IITC.2007.382352","url":null,"abstract":"In this work, we demonstrate the capability of Ecmp to meet the 45 nm and 32 nm technology node requirements in terms of topography behavior, the related electrical spread, lithography DOF budget and ULK compatibility.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127129208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Moving Away from Silicon: The Role of Interconnect in New Memory Technologies 远离硅:互连在新存储技术中的作用
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382380
D. J. Wouters
{"title":"Moving Away from Silicon: The Role of Interconnect in New Memory Technologies","authors":"D. J. Wouters","doi":"10.1109/IITC.2007.382380","DOIUrl":"https://doi.org/10.1109/IITC.2007.382380","url":null,"abstract":"New non-volatile memory concepts are based on non-Si materials, enabling new cell integration schemes. Memory elements are integrated in-between the first interconnect layers for realizing smaller cell sizes. New rectifying materials allow full decoupling from the substrate and 3-D stacking of cross-point memory arrays, moving more functionality into the back-end, and changing the role of interconnect from a passive to an active network. 3-D stacking is also pursued for Si-based memories using multiple active Si layers, with new contact technology challenges.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129170193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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