Yi-Wei Chen, Yu-Lan Chang, Yi-Cheng Chen, K. Shieh, Climbing Huang, S. F. Tzou
{"title":"牺牲硅帽层制备Ni(Pt)锗硅化物","authors":"Yi-Wei Chen, Yu-Lan Chang, Yi-Cheng Chen, K. Shieh, Climbing Huang, S. F. Tzou","doi":"10.1109/IITC.2007.382345","DOIUrl":null,"url":null,"abstract":"Ni(Pt) alloy has been implemented in the SiGe silicidation process for 65nm node CMOS device fabrication. A thin Si cap layer was introduced into the in-situ doped Si1-xGexB film stack to further enhance the thermal stability of the silicide film. The Ni(Pt) germanosilicide temperature transition curves have been studied, N-/P-FET mismatch issues have been resolved, and a robust integration flow has been developed for the 65 nm node CMOS device fabrication.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Formation of Ni(Pt) Germanosilicide Using a Sacrificial Si Cap Layer\",\"authors\":\"Yi-Wei Chen, Yu-Lan Chang, Yi-Cheng Chen, K. Shieh, Climbing Huang, S. F. Tzou\",\"doi\":\"10.1109/IITC.2007.382345\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Ni(Pt) alloy has been implemented in the SiGe silicidation process for 65nm node CMOS device fabrication. A thin Si cap layer was introduced into the in-situ doped Si1-xGexB film stack to further enhance the thermal stability of the silicide film. The Ni(Pt) germanosilicide temperature transition curves have been studied, N-/P-FET mismatch issues have been resolved, and a robust integration flow has been developed for the 65 nm node CMOS device fabrication.\",\"PeriodicalId\":403602,\"journal\":{\"name\":\"2007 IEEE International Interconnect Technology Conferencee\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE International Interconnect Technology Conferencee\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2007.382345\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE International Interconnect Technology Conferencee","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2007.382345","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Formation of Ni(Pt) Germanosilicide Using a Sacrificial Si Cap Layer
Ni(Pt) alloy has been implemented in the SiGe silicidation process for 65nm node CMOS device fabrication. A thin Si cap layer was introduced into the in-situ doped Si1-xGexB film stack to further enhance the thermal stability of the silicide film. The Ni(Pt) germanosilicide temperature transition curves have been studied, N-/P-FET mismatch issues have been resolved, and a robust integration flow has been developed for the 65 nm node CMOS device fabrication.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
