65纳米节点CMOS触点应用ALD WN工艺优化

2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI:10.1109/IITC.2007.382361

Y. Chen, T. Hung, Y. Chang, K. Shieh, C. Hsu, C. Huang, W.H. Yan, K. Ashtiani, D. Pisharoty, W. Lei, S. Chang, F. Huang, J. Collins, S. F. Tzou

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引用次数: 2

摘要

ALD氮化钨(WN)由于其高导电性和保形膜特性而成为CMOS接触衬垫/势垒应用的热门材料。由于其工艺性质与传统PVD工艺的明显差异，从薄膜性能到工艺集成的全面优化是65nm CMOS器件制造的必要条件。本文强调了这些问题，并展示了在实现CMOS触点应用的ALD WN过程中解决这些问题的方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Optimizing ALD WN Process for 65nm Node CMOS Contact Application

ALD tungsten nitride (WN) becomes attractive for CMOS contact liner/barrier application because of its highly conductive and conformal film properties. Due to the distinct differences in its process nature from the traditional PVD processes, a full optimization from film properties to process integration is necessary for the 65 nm CMOS device fabrication. This paper highlights the issues and shows the approaches to address these issues in implementing the ALD WN process for the CMOS contact application.

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2007 IEEE International Interconnect Technology Conferencee

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