BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability

Abstract

For the first time, this paper presents the results of successful integrations of Cu wiring into a production 512 Mb/90 nm design-rule stacked capacitor and recessed gate DDR (double data rate) DRAM technology, focusing on the effects of Cu integration on DRAM performance, yield, refresh time, and wafer-level reliability. 2 levels Cu interconnect (Ml single damascene and M2 dual damascene) and CVD low-k (FSG) materials have been implemented. Both the reduction in parasitic capacitance and line resistance were found to improve the operation speed of DRAM. No degradation was observed in view of normalized refresh time and yield with Cu wiring. The reliability issues with Cu integration to DRAM were systematically evaluated. In conclusion, this study demonstrates that the Cu wiring is fully compatible with the conventional DRAM and will be expected to meet the requirements of high-performance and high-speed advanced DRAM beyond sub-50 nm node.