R. Chatterjee, M. Fayolle, P. Leduc, S. Pozder, B. Jones, E. Acosta, B. Charlet, T. Enot, M. Heitzmann, M. Zussy, A. Roman, O. Louveau, S. Maitrejean, D. Louis, N. Kernevez, N. Sillon, G. Passemard, V. Po, V. Mathew, S. Garcia, T. Sparks, Zhihong Huang
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引用次数: 44
Abstract
A three-dimensional (3D) wafer-to-wafer integration technology has been developed using face-to-face dielectric wafer bonding, followed by wafer thinning and backside interconnect formation. The key technologies required for this integration include: reliable defect free direct dielectric wafer bonding, precise wafer-to-wafer alignment, backside thinning, deep inter-strata via (ISV) formation, and wafer patterning alignment across strata. Electrical measurements indicate continuity of ISV chains for all but the smallest vias.
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