Scaling of a Low Capacitance Highly Selective Self Aligned Contact Process

W. Graf, O. Genz, D. Kohler, H. Prenz, K. Schupke, A. Laessig, L. Bartholomaeus
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Abstract

A novel self aligned contact integration manufacturing method with oxide spacer is presented. Two main issues of conventional self aligned contacts are solved: high parasitic capacitive coupling through the nitride spacer and the small process window of the SAC etch. Parasitic coupling was reduced by 34 %. For the first time self aligned contacts with oxide spacer are used in DRAM production on 90 and 75 nm. The technology is seen to be extendible to 40 nm and below.
低电容高选择性自对准触点工艺的缩放
提出了一种新的氧化间隔层自对准接触集成制造方法。解决了传统自对准触点存在的两个主要问题:通过氮化物间隔片产生的高寄生电容耦合和SAC蚀刻的小工艺窗口。寄生耦合减少了34%。在90 nm和75 nm的DRAM生产中首次使用了带有氧化物间隔层的自对准触点。该技术被认为可扩展到40纳米及以下。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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