H. Kunishima, M. Tagami, T. Shin, Y. Goto, K. Oshima, T. Nishimura, Y. Miyamori, Y. Enomoto, T. Ema, N. Yamada, K. Akiyama, N. Okada
{"title":"Study on Effect of Via Contour Distortion on Via Micro-void Formation in 45nm-node Process","authors":"H. Kunishima, M. Tagami, T. Shin, Y. Goto, K. Oshima, T. Nishimura, Y. Miyamori, Y. Enomoto, T. Ema, N. Yamada, K. Akiyama, N. Okada","doi":"10.1109/IITC.2007.382378","DOIUrl":"https://doi.org/10.1109/IITC.2007.382378","url":null,"abstract":"We have investigated micro-void formation mechanism in vias at 45 nm-node using OBIRCH method and SEM analysis, and found that micro-void formation is induced by via contour distortion. We have also clarified the correlation between edge roughness of a via pattern and micro-void formation. From this, we conclude that via edge roughness suppression is the key technology for robust interconnects fabrication in 45 nm-node and beyond.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126874618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Van Olmen, S. List, Z. Tokei, L. Carbonell, S. Brongersma, H. Volders, E. Kunnen, N. Heylen, I. Ciofi, A. Khandelwal, J. Gelatos, T. Mandrekar, P. Boelen
{"title":"Cu Resistivity Scaling Limits for 20nm Copper Damascene Lines","authors":"J. Van Olmen, S. List, Z. Tokei, L. Carbonell, S. Brongersma, H. Volders, E. Kunnen, N. Heylen, I. Ciofi, A. Khandelwal, J. Gelatos, T. Mandrekar, P. Boelen","doi":"10.1109/IITC.2007.382338","DOIUrl":"https://doi.org/10.1109/IITC.2007.382338","url":null,"abstract":"Two of the most important questions concerning the future of interconnects are 1) how scalable is the damascene process to extremely narrow trenches and 2) what is the resistivity of Cu in these trenches? We attempt to answer both these questions through the generation of high aspect ratio, rectangular cross section trenches as narrow as 20 nm using a novel sacrificial Si FIN process flow. To fill such aggressive geometries, we also explore advanced PVD and ALD barrier and seed processes. We find significant electrical yields for 25 to 35 nm test structures with resistivities as predicted by sidewall scattering models.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125657540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Kim, Sunglock Lim, Hyun-Phill Kim, I. Ryu, Byung-Soo Eun, Soohyeon Kim, I. Rho, Y. Sohn, Hyosang Kang, H. Kim
{"title":"Integration and Interconnect Reliability of Warm A1 Process with CVD-A1 seed layer deposited using a novel precursor of TMAAB (trimethylarninealane borane)","authors":"C. Kim, Sunglock Lim, Hyun-Phill Kim, I. Ryu, Byung-Soo Eun, Soohyeon Kim, I. Rho, Y. Sohn, Hyosang Kang, H. Kim","doi":"10.1109/IITC.2007.382336","DOIUrl":"https://doi.org/10.1109/IITC.2007.382336","url":null,"abstract":"Al-plug process using chemical vapor deposited (CVD) Al seed layer prepared with trimethylaminealane borane (TMAAB) as a precursor lias been developed for sub-60 mn design-rule dynamic random access memory (DRAM). In terms of the precursor stability and the particle generation performance, the TMAAB is better as compared to methylpyrrolidine alane (MPA) due to the depression of (AIH3)x polymer formation which generates particle. Integration challenges of Al-plug process related to via-filling were successfully overcome and the device speed was improved compared to W-plug process. The yield and interconnect reliability comparable to W-pfug have been achieved in multi-level-metallization.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115516515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Leduca, F. de Crécy, M. Fayolle, B. Charlet, T. Enot, M. Zussy, B. Jones, J. Barbe, N. Kernevez, N. Sillon, S. Maitrejean, D. Louisa
{"title":"Challenges for 3D IC integration: bonding quality and thermal management","authors":"P. Leduca, F. de Crécy, M. Fayolle, B. Charlet, T. Enot, M. Zussy, B. Jones, J. Barbe, N. Kernevez, N. Sillon, S. Maitrejean, D. Louisa","doi":"10.1109/IITC.2007.382392","DOIUrl":"https://doi.org/10.1109/IITC.2007.382392","url":null,"abstract":"In this contribution, two main challenges for wafer-to wafer 3D integration are investigated: bonding quality (including wafer-to-wafer alignment) and thermal management. The bonding process considered in this study is direct SiO2/SiO2 hydrophilic bonding. It is shown that, after process optimization, lower than 1.5 mum misalignment was achieved without significant bonding defects. In a second part, a 3D thermal modeling was done to estimate the temperature increase in a two-stratum 3D integration. Local (3D) and global (ID) modeling contribution to the maximum temperature are discussed. It is shown that, thermal resistance due to local 3D effects can be higher than ID thermal resistance. However, thermal effects seem to be manageable.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116340203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Advanced Cu/Low-k BEOL Integration, Reliability, and Extendibility","authors":"D. Edelstein","doi":"10.1109/IITC.2007.382347","DOIUrl":"https://doi.org/10.1109/IITC.2007.382347","url":null,"abstract":"This talk will be a detailed discussion of technical aspects of Cu BEOL wiring that may be helpful or essential to preserve it successful migration path. The focus will be on BEOL architecture, integration techniques, their impact on reliability, and their outlooks for 32 nm. The talk will mainly call on new data produced by our Research and Development organizations and their associated alliances.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127340807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Thomas, A. Farcy, E. Deloffre, M. Gros-Jean, C. Perrot, D. Benoit, C. Richard, P. Caubet, S. Guillaumet, R. Pantel, B. Chenevier, J. Torres
{"title":"Impact of TaN/Ta copper barrier on full PEALD TiN/Ta2O5/TiN 3D damascene MIM capacitor performance","authors":"M. Thomas, A. Farcy, E. Deloffre, M. Gros-Jean, C. Perrot, D. Benoit, C. Richard, P. Caubet, S. Guillaumet, R. Pantel, B. Chenevier, J. Torres","doi":"10.1109/IITC.2007.382377","DOIUrl":"https://doi.org/10.1109/IITC.2007.382377","url":null,"abstract":"MIM capacitors are widely integrated for RF and analog applications. A high density full PEALD TiN/Ta2O5/TiN capacitor is integrated among copper interconnect following an innovative 3D damascene architecture. The impact of a TaN/Ta layer, introduced to avoid Cu diffusion, on both TiN electrode properties and integrated MIM stack performance is studied. Unexpected lower current was obtained without the barrier layer. As a result, up to 17 fF/mum2 capacitance densities were achieved with breakdown voltage over 15 V and excellent voltage linearity.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128255549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Kondo, M. Shiohara, K. Maruyama, K. Fukaya, K. Yamada, S. Ogawa, S. Saito
{"title":"Effect of the Hydrophilic-Lipophilic Balance (HLB) of Surfactants Included in the Post-CMP Cleaning Chemicals on Porous SiOC Direct CMP","authors":"S. Kondo, M. Shiohara, K. Maruyama, K. Fukaya, K. Yamada, S. Ogawa, S. Saito","doi":"10.1109/IITC.2007.382381","DOIUrl":"https://doi.org/10.1109/IITC.2007.382381","url":null,"abstract":"To reduce the effective k-value for the 45-nm node, direct CMP of a porous SiOC film without a protective cap layer is required. The hydrophilic-lipophilic balance (HLB) of a surfactant included in the post-CMP cleaning chemical was found to be a parameter that determines SiOC film damage and cleaning ability after direct CMP. To suppress the k-value increase and watermark generation, we need to reduce the chemical and mechanical stress of the barrier metal CMP slurry and brush scrub cleaning. Moreover, IPA (or glycolether) cleaning and H2/He remote plasma treatment are an effective restoring treatment after direct CMP.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127019570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Gallitre, L. Gosset, A. Farcy, B. Blampey, R. Gras, C. Bermond, B. Fléchet, J. Torres
{"title":"Performance predictions of prospective air gap architectures for the 22 nm node","authors":"M. Gallitre, L. Gosset, A. Farcy, B. Blampey, R. Gras, C. Bermond, B. Fléchet, J. Torres","doi":"10.1109/IITC.2007.382374","DOIUrl":"https://doi.org/10.1109/IITC.2007.382374","url":null,"abstract":"With technological developments towards 22 nm node ICs, integration and process issues will be critical for signal propagation on interconnects. Air gap architecture, as a potential alternative to porous dielectrics, is thus analyzed for two SiO2 sacrificial approaches. Thanks to electromagnetic and time-domain simulations, extraction of barrier properties and dimensions limits regarding capacitance, delay and crosstalk parameters is realized, leading to the proposal of a specific stack as a global solution to this problematic.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123701949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Air-gap transmission lines for multiprocessor interconnects on FR-4 and BT substrates","authors":"T. Spencer, P. Kohl","doi":"10.1109/IITC.2007.382344","DOIUrl":"https://doi.org/10.1109/IITC.2007.382344","url":null,"abstract":"The fabrication and characterization of low loss parallel plate and microstrip lines with an air dielectric layer is described. The lines are characterized by capacitance and loss tangent at 10 kHz and 100 kHz and by S-parameters up to 10 GHz. The inclusion of the air-gap significantly reduced the loss tangent and lowered the dielectric constant to between 1.5 and 1.8. More complicated transmission line structures could be fabricated using the described techniques.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115086454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Usami, C. Maruyama, M. Tagami, K. Watanabe, T. Kameshima, H. Masuda, M. Shimada, A. Gawase, Y. Kagawa, N. Nakamura, H. Miyajima, H. Naruse, Y. Enomoto, T. Kitano, M. Sekine
{"title":"A Study of Adhesion and Improvement of Adhesion Energy Using Hybrid Low-k (porous-PAr/ porous-SiOC(k=2.3/2.3)) Structures with Multi-layered Cu Interconnects for 45-nm Node Devices","authors":"T. Usami, C. Maruyama, M. Tagami, K. Watanabe, T. Kameshima, H. Masuda, M. Shimada, A. Gawase, Y. Kagawa, N. Nakamura, H. Miyajima, H. Naruse, Y. Enomoto, T. Kitano, M. Sekine","doi":"10.1109/IITC.2007.382358","DOIUrl":"https://doi.org/10.1109/IITC.2007.382358","url":null,"abstract":"Adhesion tests for a real Cu/low-k patterned structure were studied for 45-nm node devices. Results from 4 point-bending (4PB) and modified edge lift-off tests (m-ELT) were compared. Cu dual damascene interconnects structures with stacked hybrid low-k which is porous-poly-arylene(p-PAr)/porous-SiOC(p-SiOC) (k=2.3/2.3) were evaluated. Peel-off occurred in different locations in the real patterned structures subjected to the m-ELT test and in the structures subjected to the 4PB test. In addition, the adhesion energy (Gc: interface fracture energy) of the peeled-off interfaces was improved (Ge ges1.6x) by different treatment processes.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128725949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}